A reconfigurable pattern matching hardware implementation using on-chip RAM-based FSM

The use of synthesizable reconfigurable IP cores has increasingly become a trend in System on Chip (SoC) designs because of their flexibility and powerful functionality. The market introduction of multi-featured platform FPGAs equipped with embedded memory and processor blocks has further expanded the possibility of utilizing dynamic reconfiguration to improve overall system adaptability to meet varying product requirements. In this paper, a reconfigurable hardware implementation for pattern matching using Finite State machine (FSM) is proposed. The FSM design is RAM-based and is reconfigured on the fly through altering memory contents only. An embedded processor is used for orchestrating run time reconfiguration. Experimental results show that the system can reconfigure itself based on a new incoming pattern and perform the text search without the need of a host processor. Results also proved that each search iteration was executed in one clock cycle and the maximum achievable clock frequency is independent of search pattern length.

[1]  Mahmood Ahmadi,et al.  Reconfigurable computing architecture survey and introduction , 2009, 2009 2nd IEEE International Conference on Computer Science and Information Technology.

[2]  Haibo Wang,et al.  Self-addressable memory-based FSM: a scalable intrusion detection engine , 2009, IEEE Network.

[3]  Ivan Gonzalez,et al.  Ciphering algorithms in MicroBlaze-based embedded systems , 2006 .

[4]  A. Yurdakul,et al.  Dynamic Partial Self-Reconfiguration on Spartan-III FPGAs via a Parallel Configuration Access Port ( PCAP ) , 2008 .

[5]  Eric McDonald.  Runtime FPGA Partial Reconfiguration , 2008, 2008 IEEE Aerospace Conference.

[6]  Thierry Lecroq,et al.  Exact string matching algorithms , 1997 .

[7]  S. Bayar,et al.  Self-reconfiguration on Spartan-III FPGAs with compressed partial bitstreams via a parallel configuration access port (cPCAP) core , 2008, 2008 Ph.D. Research in Microelectronics and Electronics.

[8]  Viktor K. Prasanna,et al.  String matching on multicontext FPGAs using self-reconfiguration , 1999, FPGA '99.

[10]  João Canas Ferreira,et al.  Run-time reconfiguration support for FPGAs with embedded CPUs: the hardware layer , 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

[11]  N. Miyamoto,et al.  A 1.6mm2 4,096 logic elements multi-context FPGA core in 90nm CMOS , 2008, 2008 IEEE Asian Solid-State Circuits Conference.

[12]  Bambang Siswoyo.  Spartan-3 Starter Kit Board User Guide , 2011 .

[13]  Andreas Dandalis,et al.  Efficient Self-Reconfigurable Implementations Using On-chip Memory , 2000, FPL.

[14]  Wim Vanderbauwhede,et al.  Implementation of Finite State Machines on a Reconfigurable Device , 2007, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007).

[15]  Valery Sklyarov.  Reconfigurable models of finite state machines and their implementation in FPGAs , 2002, J. Syst. Archit..

[16]  Olivier Sentieys,et al.  Efficient dynamic reconfiguration for multi-context embedded FPGA , 2008, SBCCI '08.

[17]  Jürgen Teich,et al.  (Self-)reconfigurable finite state machines: theory and implementation , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[18]  Philip James-Roxby,et al.  A Self-reconfiguring Platform , 2003, FPL.

[19]  Bertram Bussell,et al.  Parallel Processing in a Restructurable Computer System , 1963, IEEE Trans. Electron. Comput..

[20]  Donald E. Knuth,et al.  Fast Pattern Matching in Strings , 1977, SIAM J. Comput..