SOI TFET I_ON/I_OFF Enhancement via Back Biasing

The effect of back biasing on the performance of a planar tunnel field-effect transistor (TFET) implemented on a silicon-on-insulator substrate is investigated. It is found that reverse back biasing reduces the subthreshold swing SS and in- creases the range of drain current over which SS is less than (kBT/q)ln(10); hence, it is effective for improving the TFET ON/OFF current ratio for low operating voltages (≤ 0.5 V). Index Terms—Back biasing, tunnel field-effect transistor (TFET), ultra low power.

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