论文信息 - A Subthreshold SCL Based Pipelined Encoder for Ultra-Low Power 8-bit Folding/Interpolating ADC

A Subthreshold SCL Based Pipelined Encoder for Ultra-Low Power 8-bit Folding/Interpolating ADC

The subthreshold MOS source-coupled logic (STSCL) technique is of great interest for designing ultra low power circuits. In this paper we discuss the design of a pipelined encoder for an 8-bit folding and interpolating (F&I) analog-to-digital (ADC) data converter using this technique. The encoder is designed and characterized in a conventional 0.18 ¿m CMOS technology, and it is capable of operating over a wide frequency range (10 kHz-50 MHz) without the need of resizing the transistors or scaling the voltage levels. The speed and power consumption of the encoder are proportional to the bias currents of the gates. The supply voltage of the circuit can be as low as 350 mV.

A. Tajalli | Y. Leblebici | M. Beikahmadi

[1] A. Tajalli,et al. Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications , 2008, IEEE Journal of Solid-State Circuits.

[2] E. Vittoz,et al. An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications , 1995 .

[3] Edgar Sanchez-Sinencio,et al. A wide input bandwidth 7-bit 300-MSample/s folding and current-mode interpolating ADC , 2003 .

[4] R. J. van de Plassche,et al. An 8-b 650-MHz folding ADC , 1992 .

[5] Armin Tajalli,et al. Ultra-low power subthreshold current-mode logic utilising PMOS load device , 2007 .

[6] Jan M. Rabaey,et al. MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).