Phase-Adjustable Pipelining ROM-Less Direct Digital Frequency Synthesizer With a 41.66-MHz Output Frequency

A high-speed phase-adjustable read-only-memory less direct digital frequency synthesizer employing trigonometric quadruple angle formula is presented. A ten-stage pipelining architecture is employed based upon decomposition of phase operands. Spectral purity is better than -130 dBc for the worst case spurious-free dynamic range. The resolution is up to 12 bits. Most importantly, the output sinusoidal frequency is higher than 40 MHz, which is far higher than the 32-MHz requirement of Korean personal communications system, global system for mobile communications, and Bluetooth. Neither any scaling table nor error correction tables are required. The maximum error is mathematically analyzed. The word length of each multiplier is carefully selected in the digital implementation such that the error range is limited and the resolution is preserved

[1]  G. W. Kent,et al.  A high purity, high speed direct digital synthesizer , 1995, Proceedings of the 1995 IEEE International Frequency Control Symposium (49th Annual Symposium).

[2]  Ganesh Gopalakrishnan,et al.  A fast parallel squarer based on divide-and-conquer , 1997 .

[3]  Amir M. Sodagar,et al.  A pipelined ROM-less architecture for sine-output direct digital frequency synthesizers using the second-order parabolic approximation , 2001 .

[4]  Chua-Chin Wang,et al.  A 13-bit resolution ROM-less direct digital frequency synthesizer based on a trigonometric quadruple angle formula , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Amir M. Sodagar,et al.  A novel architecture for sine-output direct digital frequency synthesizers using parabolic approximation , 2000, ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445).

[6]  Shih-Lien Lu,et al.  Interpolation-based digital quadrature frequency synthesizer , 2000, Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541).

[7]  Venceslav F. Kroupa,et al.  Direct digital frequency synthesizers , 1998 .

[8]  Michael J. Flanagan,et al.  Spur-reduced digital sinusoid synthesis , 1993, IEEE Trans. Commun..

[9]  K.I. Palomaki,et al.  Direct digital frequency synthesizer architecture based on Chebyshev approximation , 2000, Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154).

[10]  V.F. Kroupa,et al.  Spurious signals in direct digital frequency synthesizers due to the phase truncation , 1999, Proceedings of the 1999 Joint Meeting of the European Frequency and Time Forum and the IEEE International Frequency Control Symposium (Cat. No.99CH36313).

[11]  G. Van Andrews,et al.  Recent progress in wideband monolithic direct digital synthesizers , 1996, 1996 IEEE MTT-S International Microwave Symposium Digest.