Full-chip interconnect power estimation and simulation considering concurrent repeater and flip-flop insertion

In this paper, we study the full-chip interconnect power modeling. We show that repeater insertion is no longer sufficient to achieve the target frequencies specified by ITRS, and develop concurrent repeater and FF insertion schemes. Considering structural interconnects, layer assignment and concurrent repeater and FF insertion for delay specification, we develop a cycle-accurate microarchitecture-level interconnect power simulation. The simulation reduces the over-estimation by up to 2.46X compared to power estimation based on purely stochastic interconnects and fixed switching factor. Furthermore, we show that interconnect pipelining has a lower IPC but can improve throughput by up to 2.03X. This indicates that the traditional design flow optimizing IPC and clock frequency separately may no longer be valid.

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