Multi-Gbps FPGA-Based Low Density Parity Check (LDPC) Decoder Design

A novel high-throughput (6 Gb/s), fully-parallel FPGA-based 1200-bit rate-1/2 Low Density Parity Check (LDPC) decoder design is presented. The decoder features a PEG- based regular (6,3) code and a modified min-sum algorithm that improves performance without any additional hardware overhead.

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