A new dual-material double-gate (DMDG) nanoscale SOI MOSFET-two-dimensional analytical modeling and simulation

In this paper, we present the unique features exhibited by a modified asymmetrical double-gate (DG) silicon-on-insulator (SOI) MOSFET. The proposed structure is similar to that of the asymmetrical DG SOI MOSFET with the exception that the front gate consists of two materials. The resulting modified structure, i.e., a dual-material double-gate (DMDG) SOI MOSFET, exhibits significantly reduced short-channel effects (SCEs) when compared with the DG SOI MOSFET. SCEs in this structure have been studied by developing an analytical model. The model includes the calculation of the surface potential, electric field, threshold voltage, and drain-induced barrier lowering. A model for the drain current, transconductance, drain conductance, and voltage gain is also discussed. It is seen that SCEs in this structure are suppressed because of the perceivable step in the surface-potential profile, which screens the drain potential. We further demonstrate that the proposed DMDG structure provides a simultaneous increase in the transconductance and a decrease in the drain conductance when compared with the DG structure. The results predicted by the model are compared with those obtained by two-dimensional simulation to verify the accuracy of the proposed analytical model.

[1]  F. Balestra,et al.  Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance , 1987, IEEE Electron Device Letters.

[2]  Toshihiro Sugii,et al.  Analytical Models for n ++ -p Double-Gate SO1 MOSFET' s , 1995 .

[3]  T. Sugii,et al.  Analytical models for n/sup +/-p/sup +/ double-gate SOI MOSFET's , 1995 .

[4]  Tetsu Tanaka,et al.  Analytical Models for Symmetric Thin-Film Double-Gate Silicon-on-Insulator Metal-Oxide-Semiconductor-Field-Effect-Transistors , 1993 .

[5]  Yuan Taur,et al.  Device scaling limits of Si MOSFETs and their application dependencies , 2001, Proc. IEEE.

[6]  C. Hu,et al.  Observation of velocity overshoot in silicon inversion layers , 1993, IEEE Electron Device Letters.

[7]  Y. Tosaka,et al.  Scaling theory for double-gate SOI MOSFET's , 1993 .

[8]  T. Sugii,et al.  Analytical threshold voltage model for short channel double-gate SOI MOSFETs , 1996 .

[9]  W. Lai,et al.  The Vertical Replacement-Gate (VRG) MOSFET: a 50-nm vertical MOSFET with lithography-independent gate length , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[10]  Y. Tosaka,et al.  Analytical surface potential expression for thin-film double-gate SOI MOSFETs , 1994 .

[11]  R. Rios,et al.  PCIM: a physically based continuous short-channel IGFET model for circuit simulation , 1994 .

[12]  R. Pierret,et al.  Dual-gate operation and volume inversion in n-channel SOI MOSFET's , 1992, IEEE Electron Device Letters.

[13]  Xing Zhou,et al.  A simple and unambiguous definition of threshold voltage and its implications in deep-submicron MOS device modeling , 1999 .

[14]  Juan Bautista Roldán,et al.  A model for the drain current of deep submicrometer MOSFETs including electron-velocity overshoot , 1998 .

[15]  April S. Brown,et al.  DC and RF performance of 0.1 mu m gate length Al/sub 0.48/In/sub 0.52/As-Ga/sub 0.38/In/sub 0.62/As pseudomorphic HEMTs , 1988, Technical Digest., International Electron Devices Meeting.

[16]  Tetsu Tanaka,et al.  Fabrication of Double-Gate Thin-Film SOI MOSFETs Using Wafer Bonding and Polishing , 1991 .

[17]  Juan Bautista Roldán,et al.  Modeling effects of electron-velocity overshoot in a MOSFET , 1997 .

[18]  D. Kern,et al.  High transconductance and velocity overshoot in NMOS devices at the 0.1- mu m gate-length level , 1988, IEEE Electron Device Letters.

[19]  T. Sugii,et al.  Analytical threshold voltage model for short channel n/sup +/-p/sup +/ double-gate SOI MOSFETs , 1996 .

[20]  H.I. Smith,et al.  Observation of electron velocity overshoot in sub-100-nm-channel MOSFET's in Silicon , 1985, IEEE Electron Device Letters.

[21]  M. V. Fischetti,et al.  Monte Carlo simulation of a 30 nm dual-gate MOSFET: how short can Si go? , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[22]  M. J. Kumar,et al.  Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review , 2004, IEEE Transactions on Device and Materials Reliability.

[23]  K. K. Young Short-channel effect in fully depleted SOI MOSFETs , 1989 .

[24]  Tetsu Tanaka,et al.  Analysis of p/sup +/ poly Si double-gate thin-film SOI MOSFETs , 1991, International Electron Devices Meeting 1991 [Technical Digest].

[25]  Xing Zhou,et al.  Exploring the novel characteristics of hetero-material gate field-effect transistors (HMGFETs) with gate-material engineering , 2000 .

[26]  H.I. Smith,et al.  Electron velocity overshoot at room and liquid nitrogen temperatures in silicon inversion layers , 1988, IEEE Electron Device Letters.

[27]  Thomas J. Watson,et al.  High Transconductance and Velocity Overshoot in NMOS Devices at the 0. l-pm Gate-Length Level , 1988 .

[28]  Robert W. Dutton,et al.  An analytical drain current model for short-channel fully-depleted ultrathin silicon-on-insulator NMOS devices , 1995 .

[29]  T. Sugii,et al.  Scaling-parameter-dependent model for subthreshold swing S in double-gate SOI MOSFET's , 1994, IEEE Electron Device Letters.

[30]  Xing Zhou,et al.  A novel hetero-material gate (HMG) MOSFET for deep-submicron ULSI technology , 1998 .

[31]  J. Colinge,et al.  Silicon-on-insulator 'gate-all-around device' , 1990, International Technical Digest on Electron Devices.

[32]  Ken K. Chin,et al.  Dual-material gate (DMG) field effect transistor , 1999 .

[33]  M.J. Kumar,et al.  Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs , 2004, IEEE Transactions on Electron Devices.