A video signal processor for MIMD multiprocessing

The video signal processor AxPe1280V has been developed for implementation of different video coding applications according to standards like ITU-T H.261/H.263, and ISO MPEG-1I2. It consists of a RISC processor supplemented by a coprocessor for convolution-like low-level tasks. RISC and coprocessor have been implemented in a standard cell design combined with full-custom modules. The processor was fabricated in a 0.5 /spl mu/m CMOS technology and has a die size of 82 mm/sup 2/. It provides a peak performance of more than 1 giga arithmetic operations per second (GOPS) at 66 MHz. For processing of very computation-intensive algorithms or high data rates, several processors can be bus-connected to form a MIMD multiprocessor system.

[1]  Itu-T.  Video coding for low bitrate communication , 1996 .

[2]  Peter Pirsch,et al.  Architecture and VLSI implementation of a RISC core for a monolithic video signal processor , 1994, Proceedings of 1994 IEEE Workshop on VLSI Signal Processing.

[3]  J. Otterstedt,et al.  A 16 cm/sup 2/ monolithic multiprocessor system integrating 9 video signal-processing elements , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[4]  Y. Okada,et al.  An 80 mm/sup 2/ MPEG2 audio/video decode LSI , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[5]  P. Pirsch,et al.  Advances in picture coding , 1985, Proceedings of the IEEE.

[6]  K. Rijkse,et al.  H.263: video coding for low-bit-rate communication , 1996, IEEE Commun. Mag..

[7]  B. Koenemann,et al.  Built-in logic block observation techniques , 1979 .