A Chopper Stabilized CMOS Analog Multiplier with Ultra Low DC Offsets

As with many analog building blocks, DC offsets limit the accuracy of analog multipliers. Chopper stabilization, long applied to precision amplifiers, has been recently modified to be applicable to analog multiplication (Dawson and Lee, 2003). In this paper we present a general approach to chopper stabilization for analog multiplication. An IC fabricated in National Semiconductor's 0.18mum process allowed us to characterize an array of the new multipliers, which represents the first thorough experimental characterization of the new technique. The prototype circuits exhibit an average output offset of 204muV, with a standard deviation of 23muV, while consuming 181muW of power each. These are the lowest reported measured offsets in the DC analog multiplier literature

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