Easily testable PLA-based finite state machines

A synthesis procedure, which begins with a state transition graph description of a sequential machine and produces an optimized, easily testable PLA (programmable logic array) based logic implementation, is outlined. A procedure is proposed for constrained state assignment and logic optimization that guarantee testability for all combinationally irredundant crosspoint faults in a PLA-based finite-state machine. No direct access to the flip-flops is required. The test sequences to detect these faults can be obtained using combinational test generation techniques alone. This procedure thus represents an alternative to a scan design methodology. Results are presented to illustrate the efficacy of this procedure. The area/performance penalties in return for easy testability are small.<<ETX>>

[1]  Melvin A. Breuer,et al.  Diagnosis and Reliable Design of Digital Systems , 1977 .

[2]  Melvin A. Breuer A Random and an Algorithmic Technique for Fault Detection Test Generation for Sequential Circuits , 1971, IEEE Transactions on Computers.

[3]  John Grason,et al.  RTG: Automatic Register Level Test Generator , 1985, 22nd ACM/IEEE Design Automation Conference.

[4]  Alberto L. Sangiovanni-Vincentelli,et al.  MUSTANG: state assignment of finite state machines targeting multilevel logic implementations , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Kozo Kinoshita,et al.  A Design of Programmable Logic Arrays with Universal Tests , 1981, IEEE Transactions on Computers.

[6]  Alberto L. Sangiovanni-Vincentelli,et al.  Irredundant sequential machines via optimal logic synthesis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Alberto Sangiovanni-Vincentelli,et al.  PLATYPUS: A PLA Test Pattern Generation Tool , 1985, DAC 1985.

[8]  Shianling Wu,et al.  A Sequential Circuit Test Generation System , 1985, ITC.

[9]  Alberto L. Sangiovanni-Vincentelli,et al.  Synthesis and optimization procedures for fully and easily testable sequential machines , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[10]  Kurt Keutzer,et al.  Boolean minimization and algebraic factorization procedures for fully testable sequential machines , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[11]  D. C. King Diagnosis and reliable design of digital systems , 1977 .

[12]  M. Ligthart,et al.  A fault model for PLAs , 1989, [1989] Proceedings of the 1st European Test Conference.

[13]  Eric Lindbloom,et al.  A Heuristic Test-Pattern Generator for Programmable Logic Arrays , 1980, IBM J. Res. Dev..

[14]  Daniel L. Ostapko,et al.  Fault Analysis and Test Generation for Programmable Logic Arrays (PLA's) , 1979, IEEE Transactions on Computers.

[15]  Masahiko Kawamura,et al.  Test generation by activation and defect-drive (TEGAD) , 1985, Integr..

[16]  Thomas W. Williams,et al.  A logic design structure for LSI testability , 1977, DAC '77.

[17]  Robert K. Brayton,et al.  Optimal State Assignment for Finite State Machines , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[18]  Charles W. Cha A Testing Strategy for PLAs , 1978, 15th Design Automation Conference.

[19]  Robert K. Brayton,et al.  Multi-level logic minimization using implicit don't cares , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  Srinivas Devadas,et al.  Redundancies and don't cares in sequential logic synthesis , 1990, J. Electron. Test..

[21]  Eric Lindbloom,et al.  The Weighted Random Test-Pattern Generator , 1975, IEEE Transactions on Computers.