A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs
暂无分享,去创建一个
[1] Keiichi Higeta,et al. Built-in self-test for GHz embedded SRAMs using flexible pattern generator and new repair algorithm , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).
[2] W. Kent Fuchs,et al. Efficient Spare Allocation in Reconfigurable Arrays , 1986, 23rd ACM/IEEE Design Automation Conference.
[3] Yervant Zorian. Embedded Memory Test & Repair : Infrastructure IP for SOC Yield Yervant Zorian Virage Logic , 2002 .
[4] Jin-Fu Li,et al. A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap , 2006, Proceedings of the Design Automation & Test in Europe Conference.
[5] Alfredo Benso,et al. A programmable BIST architecture for clusters of multiple-port SRAMs , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).
[6] Yervant Zorian,et al. Built in self repair for embedded high density SRAM , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).
[7] Jin-Fu Li,et al. A built-in self-repair design for RAMs with 2-D redundancy , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[8] Yervant Zorian,et al. Embedded-memory test and repair: infrastructure IP for SoC yield , 2003, IEEE Design & Test of Computers.
[9] Jin-Fu Li,et al. Built-in redundancy analysis for memory yield improvement , 2003, IEEE Trans. Reliab..
[10] Rochit Rajsuman. Design and Test of Large Embedded Memories: An Overview , 2001, IEEE Des. Test Comput..
[11] Alfredo Benso,et al. An on-line BIST RAM architecture with self-repair capabilities , 2002, IEEE Trans. Reliab..
[12] Jin-Fu Li,et al. A simulator for evaluating redundancy analysis algorithms of repairable embedded memories , 2002, Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002).
[13] Jin-Fu Li,et al. Memory fault diagnosis by syndrome compression , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.
[14] Joseph Rayhawk,et al. At-speed built-in self-repair analyzer for embedded word-oriented memories , 2004, 17th International Conference on VLSI Design. Proceedings..
[15] Ming-Chang Tsai,et al. BRAINS: a BIST compiler for embedded memories , 2000, Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
[16] Jin-Fu Li,et al. An Infrastructure IP for Repairing Multiple RAMs in SOCs , 2006, 2006 International Symposium on VLSI Design, Automation and Test.
[17] Francky Catthoor,et al. Guest Editors' Intoduction: The New World of Large Embedded Memories , 2001, IEEE Des. Test Comput..
[18] Nadir Achouri,et al. Optimal reconfiguration functions for column or data-bit built-in self-repair , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.
[19] Steffen Paul,et al. Memory built-in self-repair using redundant words , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).
[20] Cheng-Wen Wu,et al. A processor-based built-in self-repair design for embedded memories , 2003, 2003 Test Symposium.
[21] Hideto Hidaka,et al. A built-in self-repair analyzer (CRESTA) for embedded DRAMs , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).
[22] M. Nicolaidis,et al. Dynamic Data-bit Memory Built-In Self- Repair , 2003, ICCAD 2003.
[23] Dilip K. Bhavsar. An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264 , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).
[24] W. Kent Fuchs,et al. Efficient Spare Allocation for Reconfigurable Arrays , 1987 .