Design tradeoff for SiGe 0.35-μm BiCMOS low-power and high figure-of-merit LNA

A 5.4-mW ultra-low dc power low-noise amplifier (LNA) at 5.5 GHz, based on 0.35-μm BiCMOS technology, is presented. The trade-off between the NF and linearity for LNA circuit design has been investigated. Furthermore, the use of the HBT-cascade-MOS methodology simultaneously satisfies the trade-off between the noise figure (NF) and linearity of the LNA. This amplifier achieves a gain/NF × PDC ratio figure of merit of 0.774 (1/mW), which is the best reported at the 5–6-GHz band, and is suitable for wireless LAN applications. © 2005 Wiley Periodicals, Inc. Microwave Opt Technol Lett 47: 65–68, 2005; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.21083

[1]  A.A. Abidi,et al.  A 2.4-GHz low-IF receiver for wideband WLAN in 6-/spl mu/m CMOS-architecture and front-end , 2000, IEEE Journal of Solid-State Circuits.

[2]  Lawrence E. Larson,et al.  Silicon technology tradeoffs for radio-frequency/mixed-signal (quote)systems-on-a-chip(quote) , 2003 .

[3]  S.P. Voinigescu,et al.  5.8 GHz and 12.6 GHz Si bipolar MMICs , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[4]  Hans Hjelmgren,et al.  Small-signal substrate resistance effect in RF CMOS identified through device simulations , 2001 .

[5]  Chorng-Kuang Wang,et al.  A 5.8-GHz two-stage high-linearity low-voltage low noise amplifier in a 0.35-/spl mu/m CMOS technology [WLANs] , 2002, 2002 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium. Digest of Papers (Cat. No.02CH37280).

[6]  Shen-Iuan Liu,et al.  Low-voltage CMOS low-noise amplifier using planar-interleaved transformer , 2001 .

[7]  J. Cressler SiGe HBT technology: a new contender for Si-based RF and microwave circuit applications , 1998 .

[8]  R. Gotzfried,et al.  RFIC's for mobile communication systems using SiGe bipolar technology , 1998 .

[9]  B. Schiffer,et al.  On-chip matched 5.2 and 5.8 GHz differential LNAs fabricated using 0.35 [micro sign]m CMOS technology , 1999 .

[10]  Piet Wambacq,et al.  Distortion analysis of analog integrated circuits , 1998 .

[11]  Sang-Gug Lee,et al.  A 5.2-GHz LNA in 0.35-μm CMOS utilizing inter-stage series resonance and optimizing the substrate resistance , 2003, IEEE J. Solid State Circuits.

[12]  Xi Li,et al.  A comparison of CMOS and SiGe LNA's and mixers for wireless LAN application , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).