Genetic-Algorithm-Based FPGA Architectural Exploration Using Analytical Models

FPGA architectural optimization has emerged as one of the most important digital design challenges. In recent years, experimental methods have been replaced by analytical ones to find the optimized architecture. Time is the main reason for this replacement. Conventional Geometric Programming (GP) is a routine framework to solve analytical models, including area, delay, and power models. In this article, we discuss the application of the Genetic Algorithm (GA) to the design of FPGA architectures. The performance model has been integrated into the Genetic Algorithm framework in order to investigate the impact of various architectural parameters on the performance efficiency of FPGAs. This way, we are able to rapidly analyze FPGA architectures and select the best one. The main advantages of using GA versus GP are concurrency and speed. The results show that concurrent optimization of high-level architecture parameters, including lookup table size (K) and cluster size (N), and low-level parameters, like scaling of transistors, is possible for GA, whereas GP does not capture K and N under its concurrency and it needs to exhaustively search all possible combinations of K and N. The results also show that more than two orders of magnitude in runtime improvement in comparison with GP-based analysis is achieved.

[1]  Zoltan Baruch.  Genetic Algorithm for FPGA Placement , 2003 .

[2]  Steven J. E. Wilton,et al.  A detailed power model for field-programmable gate arrays , 2005, TODE.

[3]  S. Yang,et al.  Logic Synthesis and Optimization Benchmarks User Guide Version 3.0 , 1991 .

[4]  Hai Zhou,et al.  Parallel CAD: Algorithm Design and Programming Special Section Call for Papers TODAES: ACM Transactions on Design Automation of Electronic Systems , 2010 .

[5]  Steven J. E. Wilton,et al.  Concurrently optimizing FPGA architecture parameters and transistor sizing: Implications for FPGA design , 2009, 2009 International Conference on Field-Programmable Technology.

[6]  Wayne Luk,et al.  An Analytical Model Relating FPGA Architecture to Logic Density and Depth , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Lei Zhou,et al.  FPGA segmented channel routing using genetic algorithms , 2005, 2005 IEEE Congress on Evolutionary Computation.

[8]  M. Yang,et al.  FPGA placement using genetic algorithm with simulated annealing , 2005, 2005 6th International Conference on ASIC.

[9]  Bijan Alizadeh,et al.  Analytical performance model for FPGA-based reconfigurable computing , 2015, Microprocess. Microsystems.

[10]  Bijan Alizadeh,et al.  An analytical dynamic and leakage power model for FPGAs , 2014, 2014 22nd Iranian Conference on Electrical Engineering (ICEE).

[11]  Steven J. E. Wilton,et al.  Wirelength modeling for homogeneous and heterogeneous FPGA architectural development , 2009, FPGA '09.

[12]  Vaughn Betz,et al.  Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.

[13]  Kenneth A. De Jong,et al.  Are Genetic Algorithms Function Optimizers? , 1992, PPSN.

[14]  Philip Heng Wai Leong,et al.  A detailed delay path model for FPGAs , 2009, 2009 International Conference on Field-Programmable Technology.

[15]  Steven J. E. Wilton,et al.  An analytical model relating FPGA architecture and place and route runtime , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[16]  Zied Marrakchi,et al.  A Top-Down Optimization Methodology for Mutually Exclusive Applications , 2014, Int. J. Reconfigurable Comput..

[17]  Peter Y. K. Cheung,et al.  FPGA Architecture Optimization Using Geometric Programming , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[18]  Jonathan Rose,et al.  Modeling routing demand for early-stage FPGA architecture development , 2008, FPGA '08.