Design of High Performance PFD(Phase Frequency Detector) Circuit for PLL(Phase Locked Loop)

PLL(Phase Locked Loop) are widely used circuit technique in modern electronic systems. In this paper, We propose the PLL using high performance PFD(Phase Frequency Detector). We design the PFD by using TSPC (True Single Phase Clock)circuit to improve the performance and solve the dead-zone problem. We use CP(Charge Pump) and LP(Loop filter) for Negative feedback and current reusing in order to solve current mismatch and switch mismatch problem. The VCO(Voltage controlled Oscillator) with 5-stage differential ring oscillator. The divider is implemented by using D-type flip flops asynchronous dividing. The frequency range of VCO has from 200㎒ to 1.1㎓ and have 1.7㎓/v of voltage gain. The proposed PLL is designed by using 0.18um CMOS processor with 1.8V supply voltage. Reference input frequency is 25㎒ and VCO output frequency is 800㎒ and lock time is 8.3us. It is evaluated by using cadence spectra RF tools.