Interconnection schemes for parasitics optimization

A set of four interconnection schemes is proposed to reduce parasitic ground and coupling capacitances and thus enhance technology performance. These strategies consist in: increasing the inter-metal dielectric thicknesses, using SiOF instead of SiO2, embedding the interconnects in a low-permittivity dielectric and switching to copper metallizations with constant line resistance. The effectiveness of these schemes is checked for the capacitances of simple 2D structures, for delay, crosstalk, and consumption in standard circuit routings, and for a 32 bits adder worst case delay and consumption.