Shielding Area Optimization Under the Solution of Interconnect Crosstalk

As the technology advances into deep sub-micron era, crosstalk reduction is of paramount importance for signal integrity. Simultaneous shield insertion and net ordering (SINO) has been shown to be effective to reduce both capacitive and inductive couplings. As it introduces extra shields, area minimization is also critical for an efficient SINO algorithm. In this paper, three novel algorithms using fewer shields to solve crosstalk reduction problem with RLC noise constraint are proposed, namely, net coloring (NC), efficient middle shield insertion (EMSI) and NC+EMSI two-step algorithm. Compared with the corresponding algorithms in previous work, these algorithms can reduce shielding area up to 25.77%, 46.19%, and 7.17%, respectively, with short runtime.

[1]  Jamil Kawa,et al.  Managing on-chip inductive effects , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[2]  A. Ruehli Equivalent Circuit Models for Three-Dimensional Multiconductor Systems , 1974 .

[3]  C. L. Liu,et al.  Minimum crosstalk channel routing , 1993, ICCAD.

[4]  Jun Chen,et al.  Determination of worst-case crosstalk noise for non-switching victims in GHz+ interconnects , 2003, ASP-DAC '03.

[5]  Lei He,et al.  Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization , 2000, ISPD '00.

[6]  Jason Cong,et al.  Pseudo pin assignment with crosstalk noise control , 2000, ISPD '00.

[7]  XuMin,et al.  Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization , 2004 .

[8]  Lei He,et al.  Modeling and Layout Optimization for On-chip Inductive Coupling , 2000 .

[9]  James D. Meindl,et al.  Compact distributed RLC interconnect models - part IV: unified models for time delay, crosstalk, and repeater insertion , 2003 .

[10]  C. L. Liu,et al.  Minimum crosstalk switchbox routing , 1994, ICCAD.

[11]  Wei Chen,et al.  Cross talk driven placement , 2003, ASP-DAC '03.

[12]  Lei He,et al.  Simultaneous shield insertion and net ordering under explicit RLC noise constraint , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[13]  Lei He,et al.  An efficient inductance modeling for on-chip interconnects , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

[14]  Dongsheng Wang,et al.  Post global routing crosstalk synthesis , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Lei He Interconnect Modeling and Design With Consideration of Inductance , 2001 .

[16]  C. Kyung,et al.  Reducing cross-coupling among interconnect wires in deep-submicron datapath design , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[17]  Jinjun Xiong,et al.  Full-chip routing optimization with RLC crosstalk budgeting , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[18]  James D. Z. Ma,et al.  Formulae and applications of interconnect estimation considering shield insertion and net ordering , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[19]  Shen Lin,et al.  Quick on-chip self- and mutual-inductance screen , 2000, Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525).