Secure hardware design against side-channel attacks

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii CHAPTER

[1]  Ariel J. Feldman,et al.  Lest we remember: cold-boot attacks on encryption keys , 2008, CACM.

[2]  Randolph D. Nelson,et al.  Probability, stochastic processes, and queueing theory - the mathematics of computer performance modeling , 1995 .

[3]  Stefan Mangard,et al.  Power analysis attacks - revealing the secrets of smart cards , 2007 .

[4]  Farid N. Najm,et al.  A survey of power estimation techniques in VLSI circuits , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[5]  Robert H. Sloan,et al.  Examining Smart-Card Security under the Threat of Power Analysis Attacks , 2002, IEEE Trans. Computers.

[6]  Kurt Keutzer,et al.  Estimation of average switching activity in combinational logic circuits using symbolic simulation , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Silvio Micali,et al.  Physically Observable Cryptography (Extended Abstract) , 2004, Theory of Cryptography Conference.

[8]  Ross J. Anderson,et al.  On a new way to read data from memory , 2002, First International IEEE Security in Storage Workshop, 2002. Proceedings..

[9]  I. Verbauwhede,et al.  A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards , 2002, Proceedings of the 28th European Solid-State Circuits Conference.

[10]  Jean-Jacques Quisquater,et al.  Information Theoretic Evaluation of Side-Channel Resistant Logic Styles , 2007, CHES.

[11]  Stefan Mangard,et al.  Successfully Attacking Masked AES Hardware Implementations , 2005, CHES.

[12]  Akhilesh Tyagi.  Energy-Privacy Trade-Offs in VLSI Computations , 2005, INDOCRYPT.

[13]  Paul C. Kocher,et al.  Differential Power Analysis , 1999, CRYPTO.

[14]  Massoud Pedram,et al.  Probabilistic error propagation in logic circuits using the Boolean difference calculus , 2008, 2008 IEEE International Conference on Computer Design.

[15]  Akhilesh Tyagi,et al.  Towards Making Private Circuits Practical: DPA Resistant Private Circuits , 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

[16]  Jean-Jacques Quisquater,et al.  ElectroMagnetic Analysis (EMA): Measures and Counter-Measures for Smart Cards , 2001, E-smart.

[17]  David Harris,et al.  CMOS VLSI Design: A Circuits and Systems Perspective , 2004 .

[18]  Irving S. Reed,et al.  A class of multiple-error-correcting codes and the decoding scheme , 1954, Trans. IRE Prof. Group Inf. Theory.

[19]  Ingrid Verbauwhede,et al.  A VLSI design flow for secure side-channel attack resistant ICs , 2005, Design, Automation and Test in Europe.

[20]  Ethem Alpaydin,et al.  Introduction to machine learning , 2004, Adaptive computation and machine learning.

[21]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[22]  Vladimir Vapnik,et al.  Statistical learning theory , 1998 .

[23]  Liwei Zhang,et al.  A Statistics-based Fundamental Model for Side-channel Attack Analysis , 2014, IACR Cryptol. ePrint Arch..

[24]  Thomas S. Messerges,et al.  Securing the AES Finalists Against Power Analysis Attacks , 2000, FSE.

[25]  Massimo Alioto,et al.  A General Power Model of Differential Power Analysis Attacks to Static Logic Circuits , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[26]  A. M. Mathai.  Quadratic forms in random variables , 1992 .

[27]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[28]  Akashi Satoh,et al.  A Compact Rijndael Hardware Architecture with S-Box Optimization , 2001, ASIACRYPT.

[29]  Stefan Mangard,et al.  Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints , 2005, CHES.

[30]  Vinod Vaikuntanathan,et al.  Inspection resistant memory: Architectural support for security from physical examination , 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).

[31]  Yuval Ishai,et al.  Private Circuits: Securing Hardware against Probing Attacks , 2003, CRYPTO.

[32]  Alexandre Yakovlev,et al.  Power balanced circuits for leakage-power-attacks resilient design , 2015, 2015 Science and Information Conference (SAI).

[33]  Akhilesh Tyagi,et al.  t-Private logic synthesis on FPGAs , 2012, 2012 IEEE International Symposium on Hardware-Oriented Security and Trust.

[34]  Emmanuel Prouff,et al.  A Generic Method for Secure SBox Implementation , 2007, WISA.

[35]  Akhilesh Tyagi,et al.  t-Private Systems: Unified Private Memories and Computation , 2014, SPACE.

[36]  Tsutomu Sasao,et al.  Representations of Discrete Functions , 2011 .

[37]  Charu C. Aggarwal,et al.  On the design and quantification of privacy preserving data mining algorithms , 2001, PODS.

[38]  Akhilesh Tyagi,et al.  Security Metrics for Power Based SCA Resistant Hardware Implementation , 2016, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID).

[39]  R. A. Leibler,et al.  On Information and Sufficiency , 1951 .

[40]  Moti Yung,et al.  A Unified Framework for the Analysis of Side-Channel Key Recovery Attacks (extended version) , 2009, IACR Cryptol. ePrint Arch..

[41]  Ingrid Verbauwhede,et al.  A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.