论文信息 - A 2.5 V 12 b 5 MSample/s pipelined CMOS ADC

A 2.5 V 12 b 5 MSample/s pipelined CMOS ADC

This 1.2 /spl mu/m, 33 mW analog-to-digital converter (ADC) demonstrates a family of power reduction techniques including a commutated feedback capacitor switching (CFCS), sharing of the second stage of an op amp between adjacent stages of a pipeline, reusing the first stage of an op amp as the comparator pre-amp, and exploiting parasitic capacitance as common-mode feedback capacitors.

Hae-Seung Lee | P.C. Yu | Hae-Seung Lee | P. Yu

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