A Logic to Specify and Verify Synchronous Transitions

This paper introduces a formalism named SINC aimed at the design and verification of synchronous concurrent systems. The components of this formalism are a transition system and a first-order linear-time temporal logic. The SINC transition system adopts a synchronous computation model, includes a method to solve write-conflicts, and represents transitions as possibly non-terminating imperative commands. The SINC logic allows for formal reasoning about SINC transition systems using compositional and modular proofs. Such features are important to the verification of a large class of systems, but they are missing in other formalisms based on transition systems and temporal logics. This paper also discusses some of the pragmatics in specifying and verifying systems using SINC, and presents extensions to deal with generic parameters and regular structures. SINC is based on the Hoare logic and the UNITY formalism.

[1]  Jorgen Staunstrup.  A formal approach to hardware design , 1994, The Kluwer international series in engineering and computer science.

[2]  Carlos Delgado Kloos,et al.  A refinement calculus for the synthesis of verified hardware descriptions in VHDL , 1997, TOPL.

[3]  Zohar Manna,et al.  Temporal verification of reactive systems - safety , 1995 .

[4]  Jean-Pierre Banâtre,et al.  Parallel Program Design , 1991, Research Directions in High-Level Parallel Programming Languages.

[5]  John Van Tassel.  Femto-VHDL : the semantics of a subset of VHDL and its embedding in the HOL proof assistant , 1993 .

[6]  Sérgio Vale Aguiar Campos,et al.  Symbolic Model Checking , 1993, CAV.

[7]  Yuri Gurevich,et al.  Evolving algebras 1993: Lipari guide , 1995, Specification and validation methods.

[8]  Yuri Gurevich,et al.  Evolving Algebras: an Attempt to Discover Semantics , 1993, Current Trends in Theoretical Computer Science.

[9]  Carlos Delgado Kloos,et al.  A simple denotational semantics, proof theory and a validation condition generator for unit-delay VHDL , 1995, Formal Methods Syst. Des..

[10]  Anish Arora,et al.  Book Review: Verification of Sequential and Concurrent Programs by Krzysztof R. Apt and Ernst-Riidiger Olderog (Springer-Verlag New York, 1997) , 1998, SIGA.

[11]  Wolfgang Müller,et al.  The semantics of behavioral VHDL '93 descriptions , 1994, EURO-DAC '94.

[12]  Randal E. Bryant,et al.  Concurrent programming , 1980, Operating Systems Engineering.

[13]  Carlos Delgado Kloos,et al.  Formal Semantics for VHDL , 1995 .

[14]  J. Davenport.  Editor , 1960 .

[15]  K. Mani Chandy,et al.  Parallel program design - a foundation , 1988 .

[16]  Lalita Jategaonkar Jagadeesan,et al.  Safety Property Verification of ESTEREL Programs and Applications to Telecommunications Software , 1995, CAV.

[17]  Carlos Delgado Kloos,et al.  Practical Formal Methods for Hardware Design , 2001, Research Reports Esprit.

[18]  Ashraf M. Salem,et al.  Denotational semantics of a synchronous VHDL subset , 1995, Formal Methods Syst. Des..

[19]  Leslie Lamport,et al.  The temporal logic of actions , 1994, TOPL.

[20]  Jayadev Misra.  A Logic for Concurrent Programming , 1994 .

[21]  Arno Schonegge,et al.  Extending Dynamic Logic for Reasoning about Evolving Algebras , 1995 .

[22]  A. Udaya Shankar,et al.  An introduction to assertional reasoning for concurrent systems , 1993, CSUR.

[23]  Laurence Pierre,et al.  Formal verification of VHDL descriptions in the Prevail environment , 1992, IEEE Design & Test of Computers.

[24]  Philip A. Wilsey,et al.  A model of VHDL for the analysis, transformation, and optimization of digital system designs , 1995, Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair.

[25]  Thomas Filkorn,et al.  The FORMAT Model Checker , 1997 .

[26]  Peter Päppinghaus,et al.  On the Logic of UNITY , 1995, Theor. Comput. Sci..

[27]  Zohar Manna,et al.  The Temporal Logic of Reactive and Concurrent Systems , 1991, Springer New York.

[28]  Vanderlei Moraes Rodrigues,et al.  A temporal logic for data-flow VHDL , 1998, Proceedings. XI Brazilian Symposium on Integrated Circuit Design (Cat. No.98EX216).