The Gilgamesh processor-in-memory architecture and its execution model

The emergence of semiconductor fabrication technology allowing a tight coupling between high-density DRAM and CMOS logic on the same chip has led to the important new class of Processor-In-Memory (PIM) architectures. Newer developments provide powerful parallel processing capabilities on the chip, exploiting the facility to load wide words in single memory accesses, and supporting complex address manipulations in the memory. Furthermore, large arrays of PIMs can be arranged into a massively parallel architecture. In this paper, we describe key features of the Gilgamesh PIM architecture developed at Caltech and JPL, and introduce an object-based execution model for this architecture based on the notion of macroservers. Macroservers are associated with a state space in which a set of lightweight threads executes asynchronously; the location and distribution of objects and data in PIM memory can be dynamically controlled. We discuss the elements of a software architecture for Gilgamesh and illustrate some aspects of macroservers by outlining a sparse matrix algorithm.