Evaluating Partial Reconfiguration for Embedded FPGA Applications

Recent advances in Xilinx’s FPGA hardware and commercial software design tools, spurred in large part by the DOD’s Joint Tactical Radio System initiative, offer the possibility of incorporating dynamic partial reconfiguration (PR) into highperformance, embedded systems outside of academic research laboratories. PR can provide the flexibility and run-time reconfigurability that no pure hardware or software solution can offer. By multiplexing the hardware resources of a single programmable device with time-independent tasks, a common architecture in DOD systems, a single FPGA can handle the same processing workload as a multi-device equivalent. This paper analyzes the performance impact of using PR to perform remote updating, an important capability often used in embedded applications.