Simultaneous Retiming and Placement for Pipelined Netlists

Although pipelining or C-slowing an FPGA-based application can potentially dramatically improve the performance, this poses a question for conventional reconfigurable architectures and CAD tools: what is the best way to support these new extra registers? While there have been multiple research efforts to address this problem, they generally impose strict architectural requirements, offer limited retiming capabilities, or require multiple iterations with no guarantees regarding feasible implementations. In this paper we introduce a new simulated annealing-based placement and retiming approach that provides the capability to aggressive apply retiming on a wide range of netlists, for arbitrary architectures, while maintaining predictable results. Our results show that for heavily pipelined applications, this methodology can produce netlists and placements with 1.65x better post-routing critical path delay as compared to the classical approach of retiming before timing-driven VPR placement, and 1.08x better than retiming before our improved timing-driven placer.

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