Low Power and Energy Efficient Single Error Correction Code using CDM logic style for IoT devices

For decades, Error Correction Codes (ECC) have been extensively used to protect the data in registers and memory from errors. The most used ECC’s are Single Error Correction (SEC) codes, which can correct a one-bit error for each word. Due to the recent scale-down in the size of technology, the demand for low power, high speed, and area & energy efficient SEC encoders and decoders have become prominent. Many applications, like IoT devices, memory storage and security applications employing SECs, need reliable hardware at low cost and low power consumption. Significant research has been going on to design efficient ECC’s for energy efficiency and cost optimization. In this paper, Cell Design Methodology (CDM) as an efficient logic style is used for optimization of ECC at the transistor level for improving circuit characteristics. A significant improvement has been recorded by comparing the performance of the SEC codes in terms of power and energy between conventional CMOS (C-CMOS) and CDM logic structures. C-CMOS and CDM standard cells of 10nm, 14nm, 16nm, and 20nm technologies are used to compare the circuit characteristics of the SEC encoder and decoder. The traditional Hamming code and Pedro’s SEC [1] have been used for effective comparison and performance analysis of the cell libraries. This analysis has shown an average improvement of 32.4% on power consumption and 30% on energy consumption by using CDM logic style over the C-CMOS structure.