The Design of a GaAs Systolic Array for an Adaptive Null Steering Beamforming Controller

Our design of the RCA GaAs systolic array beamforming control0 ler demonstrates the advantages of using a top-down approach for designing an adaptive radar system. Because of its speed and unique characteristics, the GaAs technology chosen to implement the array significantly influenced the design of the internal processor architecture. The array is configured as an SIMD machine in which each processing site communicates only with its nearest neighbors. The array is intended for use in digital radar beamforming for automatic null steering. Several systolic arrays have been proposed or constructed for similar applications. Among them are the RCA Gram-Schmidt Preprocessor,' the NOSC (Naval Ocean Systems Center) systolic array,2 and the Carnegie Mellon Warp3 machine, which was constructed in cooperation with General Electric and Honeywell. The selection of an algorithm that could adaptively generate the complex beamforming coefficient vector was the first step in our design process. Of the many such algorithms studied, including MSR3, Gram-Schmidt, and Givens, the MSR3 Algorithm was identified as offering the best combination of performance, stability, and ease of systolic implementation. Each algorithm's performance was judged by the algorithm's speed of convergence, the depth of nulls, and the shape of the antenna pattern produced. The MSR3 Algorithm became the design guide for the systolic array. The MSR3 Algorithm iteratively converges on a solution to the beamforming coefficients by minimizing the error in the energy received by the antenna. The computational core of each iteration consists of a pair ofdoubly nested DO loops; each loop has several arithmetic operations inside. Such a sequential code structure implies a two-dimensional systolic array of processors. For a doubly nested loop, a twodimensional array of processing nodes can be used in which each node corresponds to an iteration of the outer loop, and each column corresponds to an iteration ofthe inner loop. In the application, the innerarray index limit is dependent on the outerarray index, as shown in the following: