4 Reconfigurable Computing and Digital Signal Processing : Past , Present , and Future

[1]  Scott Hauck,et al.  The Chimaera reconfigurable functional unit , 1997, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Sakir Sezer,et al.  Development of a Run-Time Reconfiguration System with Low Reconfiguration Overhead , 2001, J. VLSI Signal Process..

[3]  George Varghese,et al.  Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System , 2001, J. VLSI Signal Process..

[4]  Russell Tessier,et al.  ASOC: a scalable, single-chip communications architecture , 2000, Proceedings 2000 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00622).

[5]  Alex K. Jones,et al.  A MATLAB compiler for distributed, heterogeneous, reconfigurable computing systems , 2000, Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871).

[6]  Fadi J. Kurdahi,et al.  Design and Implementation of the MorphoSys Reconfigurable Computing Processor , 2000, J. VLSI Signal Process..

[7]  N. Nazari.  A 500 Mb/s disk drive read channel in 0.25 /spl mu/m CMOS incorporating programmable noise predictive Viterbi detection and trellis coding , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[8]  G. Weinberger.  The new millennium: wireless technologies for a truly mobile society , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[9]  H. Zhang,et al.  A 1 V heterogeneous reconfigurable processor IC for baseband wireless applications , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[10]  Russell Tessier,et al.  Tolerating operational faults in cluster-based FPGAs , 2000, FPGA '00.

[11]  Naresh R. Shanbhag,et al.  Dynamic algorithm transformations (DAT)-a systematic approach to low-power reconfigurable signal processing , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[12]  A. E. Bell.  The dynamic digital disk , 1999 .

[13]  Russell Tessier.  Incremental compilation for logic emulation , 1999, Proceedings Tenth IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype (Cat. No.PR00246).

[14]  J. Othmer,et al.  Software environment for a multiprocessor DSP , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[15]  M. Budiu,et al.  PipeRench: a coprocessor for streaming multimedia acceleration , 1999, Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367).

[16]  Jean Vuillemin,et al.  A reconfigurable arithmetic array for multimedia applications , 1999, FPGA '99.

[17]  Wayne P. Burleson,et al.  Configuration cloning: exploiting regularity in dynamic DSP architectures , 1999, FPGA '99.

[18]  N.R. Shanbhag,et al.  A low-power, reconfigurable adaptive equalizer architecture , 1999, Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers (Cat. No.CH37020).

[19]  Chandra Tan,et al.  Automatic Mapping of Khoros-based Applications to Adaptive Computing Systems , 1999 .

[20]  Kurt Keutzer,et al.  Getting to the bottom of deep submicron , 1998, ICCAD '98.

[21]  Brad Hutchings,et al.  The flexibility of configurable computing , 1998 .

[22]  William J. Dally,et al.  Digital systems engineering , 1998 .

[23]  D. H. Horrocks,et al.  High level performance estimation for a primitive operator filter FPGA , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[24]  Wayne P. Burleson,et al.  Reconfiguration for power saving in real-time motion estimation , 1998, Proceedings of the 1998 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP '98 (Cat. No.98CH36181).

[25]  Patrick Schaumont,et al.  A programming environment for the design of complex high speed ASICs , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[26]  Stephen M. Scalera,et al.  The design and implementation of a context switching FPGA , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[27]  Tsuyoshi Isshiki,et al.  New FPGA architecture for bit-serial pipeline datapath , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[28]  Peter Gray,et al.  An overview of the COBRA-ABS high level synthesis system for multi-FPGA systems , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[29]  Peter M. Athanas,et al.  A run-time reconfigurable engine for image interpolation , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[30]  Laurent Moll,et al.  Hardware/software integration in solar polarimetry , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[31]  Kunle Olukotun,et al.  A quantitative analysis of reconfigurable coprocessors for multimedia applications , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[32]  Zhiyuan Li,et al.  Configuration compression for the Xilinx XC6200 FPGA , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[33]  Wayne Luk,et al.  Automating production of run-time reconfigurable designs , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[34]  Satnam Singh,et al.  Accelerating Adobe Photoshop with reconfigurable logic , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[35]  Scott McMillan,et al.  A re-evaluation of the practicality of floating-point operations on FPGAs , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[36]  Scott Hauck,et al.  The roles of FPGAs in reprogrammable systems , 1998, Proc. IEEE.

[37]  Jan M. Rabaey,et al.  VLSI design and implementation fuels the signal-processing revolution , 1998 .

[38]  Roger F. Woods,et al.  Applying an XC6200 to Real-Time Image Processing , 1998, IEEE Des. Test Comput..

[39]  Viktor K. Prasanna,et al.  Seeking Solutions in Configurable Computing , 1997, Computer.

[40]  P. Kollig,et al.  FPGA implementation of high performance FIR filters , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

[41]  Anant Agarwal,et al.  Logic emulation with virtual wires , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[42]  Wayne P. Burleson,et al.  An FPGA-based data acquisition system for a 95 GHz W-band radar , 1997, 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[43]  Jack Greenbaum,et al.  Increased FPGA capacity enables scalable, flexible CCMs: an example from image processing , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[44]  John Wawrzynek,et al.  Garp: a MIPS processor with a reconfigurable coprocessor , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[45]  John Woodfill,et al.  Real-time stereo vision on the PARTS reconfigurable computer , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[46]  Carl Ebeling,et al.  Mapping applications to the RaPiD configurable architecture , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[47]  Brad L. Hutchings,et al.  Automated target recognition on SPLASH 2 , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[48]  Peter M. Athanas,et al.  Wormhole run-time reconfiguration , 1997, FPGA '97.

[49]  Brian Von Herzen.  Signal processing at 250 MHz using high-performance FPGA's , 1997, FPGA '97.

[50]  Peter Pirsch,et al.  Architectural approaches for multimedia processors , 1997, Electronic Imaging.

[51]  Dennis L. Goeckel,et al.  Robust adaptive coded modulation for time-varying channels with delayed feedback , 1997 .

[52]  Gregory Ray Goslin,et al.  Guide to using field programmable gate arrays (FPGAs) for application-specific digital signal processing performance , 1996, Other Conferences.

[53]  Chris Dick.  FPGA based systolic array architectures for computing the discrete Fourier transform , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[54]  Todd A. Cook,et al.  Implementation of IEEE single precision floating point addition and multiplication on FPGAs , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[55]  Paul Chow,et al.  RACER: a reconfigurable constraint-length 14 Viterbi decoder , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[56]  Geoffrey Brown,et al.  A software development system for FPGA-based data acquisition systems , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[57]  Peter M. Athanas,et al.  Using rapid prototyping to teach the design of complete computing solutions , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[58]  Tsuyoshi Isshiki,et al.  Bit-serial pipeline synthesis for multi-FPGA systems with C++ design capture , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[59]  Wayne Luk,et al.  Modelling and optimising run-time reconfigurable systems , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[60]  André DeHon,et al.  MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[61]  Ralph Wittig,et al.  OneChip: an FPGA processor with reconfigurable logic , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[62]  John D. Villasenor,et al.  Configurable computing solutions for automatic target recognition , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[63]  Mark Shand,et al.  Programmable active memories: reconfigurable systems come of age , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[64]  Ian Page.  Constructing hardware-software systems from a single description , 1996, J. VLSI Signal Process..

[65]  John D. Villasenor,et al.  Video communications using rapidly reconfigurable hardware , 1995, IEEE Trans. Circuits Syst. Video Technol..

[66]  M. Horowitz,et al.  Energy dissipation in general purpose processors , 1995, 1995 IEEE Symposium on Low Power Electronics. Digest of Technical Papers.

[67]  John Gray,et al.  Use of Reconfigurability in Variable-Length Code Detection at Video Rates , 1995, FPL.

[68]  Bede Liu,et al.  An efficient bit-serial FIR filter architecture , 1995 .

[69]  Deborah Silver,et al.  Acceleration of template-based ray casting for volume visualization using FPGAs , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[70]  Mark Shand.  Flexible image acquisition using reconfigurable hardware , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[71]  Brad L. Hutchings,et al.  A dynamic instruction set computer , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[72]  Peter M. Athanas,et al.  Quantitative analysis of floating point arithmetic on FPGA based custom computing machines , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[73]  Anil K. Jain,et al.  Convolution on Splash 2 , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[74]  Poras T. Balsara,et al.  An architecture for a DSP field-programmable gate array , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[75]  P.M. Athanas,et al.  Real-Time Image Processing on a Custom Computing Platform , 1995, Computer.

[76]  Richard J. Carter,et al.  Teramac-configurable custom computing , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[77]  Massoud Pedram,et al.  Power conscious CAD tools and methodologies: a perspective , 1995, Proc. IEEE.

[78]  Edward A. Lee,et al.  Ptolemy: A Framework for Simulating and Prototyping Heterogenous Systems , 2001, Int. J. Comput. Simul..

[79]  Michael D. Smith,et al.  A high-performance microarchitecture with hardware-programmable functional units , 1994, Proceedings of MICRO-27. The 27th Annual IEEE/ACM International Symposium on Microarchitecture.

[80]  Barry S. Fagin,et al.  Field programmable gate arrays and floating point arithmetic , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[81]  Joseph B. Evans.  Efficient FIR filter architectures suitable for FPGA implementation , 1994 .

[82]  B. Box.  Field programmable gate array based reconfigurable preprocessor , 1994, Proceedings of National Aerospace and Electronics Conference (NAECON'94).

[83]  Shousheng He,et al.  FPGA implementation of FIR filters using pipelined bit-serial canonical signed digit multipliers , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

[84]  Peter Athanas,et al.  Finding lines and building pyramids with SPLASH 2 , 1994, Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines.

[85]  John Rasure,et al.  The Khoros Application Development Environment , 1994 .

[86]  Miriam Leeser,et al.  High level synthesis and generating FPGAs with the BEDROC system , 1993, J. VLSI Signal Process..

[87]  Herman Schmit,et al.  A Model and Methodology for Hardware-Software Codesign , 1993, IEEE Des. Test Comput..

[88]  Hideharu Amano,et al.  WASMII: a data driven computer on a virtual hardware , 1993, [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines.

[89]  M. Gokhale,et al.  FPGA computing in a data parallel C , 1993, [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines.

[90]  Harvey F. Silverman,et al.  Processor reconfiguration through instruction-set metamorphosis , 1993, Computer.

[91]  Jan M. Rabaey,et al.  A reconfigurable multiprocessor IC for rapid prototyping of algorithmic-specific high-speed DSP data paths , 1992 .

[92]  Joseph Varghese,et al.  An efficient logic emulation system , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[93]  Daniel P. Lopresti,et al.  Building and using a highly parallel programmable logic array , 1991, Computer.

[94]  N. Hastie,et al.  The implementation of hardware subroutines on field programmable gate arrays , 1990, IEEE Proceedings of the Custom Integrated Circuits Conference.

[95]  G. Goossens,et al.  CATHEDRAL II—a computer-aided synthesis system for digital signal processing VLSI systems , 1988 .

[96]  Edward A. Lee.  Programmable dsp architectures: part ii , 1988 .

[97]  Frank B. Manning.  Automatic test, configuration, and repair of cellular arrays , 1975 .

[98]  Richard G. Shoup.  Programmable cellular logic arrays , 1970 .

[99]  Robert C. Minnick,et al.  A Survey of Microcellular Research , 1967, JACM.

[100]  Bertram Bussell,et al.  Parallel Processing in a Restructurable Computer System , 1963, IEEE Trans. Electron. Comput..

[101]  Karuna K. Maitra,et al.  Cascaded Switching Networks of Two-Input Flexible Cells , 1962, IRE Trans. Electron. Comput..