We propose a modified Goldschimdt reciprocation algorithm for single precision computation, without using a look-up table. It is a variable latency algorithm i.e. the number of iterations depends on the input operands that provide a linear convergence. Multiplying with the dividend results division, our method requires a cycle for each iteration, performing multiply add and Booth recoding in a cycle. Initial approximation is a two's complement of the divisor, which can be performed during partial product summation. The implementation is described in IBM G5 FPU(floating point unit) and MIPS R10000 processor multiplier, evaluated and compared with conventional processors. It offers a good trade-off between performance and area, making it suitable for mobile computing applications such as PDA(personal digital assistant), UPC(ultra personal computer), mobile phone, tablet PC(personal computer) etc
[1]
Kenneth C. Yeager.
The Mips R10000 superscalar microprocessor
,
1996,
IEEE Micro.
[2]
Christopher A. Krygowski,et al.
The S/390 G5 floating-point unit
,
1999,
IBM J. Res. Dev..
[3]
David W. Matula,et al.
Recoders for Partial Compression and Rounding
,
1997
.
[4]
José Alejandro Piñeiro Riobó.
Algorithms and architectures for elementary function computation
,
2003
.
[5]
Stuart F. Oberman,et al.
Floating point division and square root algorithms and implementation in the AMD-K7/sup TM/ microprocessor
,
1999,
Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336).