Low-leakage soft error tolerant dual-port SRAM cells for cache memory applications

As transistor dimensions are reduced due to technological advances, the area constraint is becoming less restrictive, but soft error rate, leakage current, and process variation are drastically increased. Therefore, in nano-scaled CMOS technology, soft error rate, leakage current and process variation are the most important issues in designing embedded cache memory. To overcome these challenges, and based on the observation that cache-resident memory values of ordinary programs exhibit a strong bias towards zero, this paper deals with new low leakage, hardened, and read-static-noise-margin-free SRAM memory cells for nano-scaled CMOS technology. These cells are completely hardened and cannot flip from particle strikes at the sensitive cell nodes. Furthermore, these new SRAM cells have free read-static-noise-margin, such that transistor mismatching, due to process variation, cannot destroy stored-data of the cells during read operation. The new cells retain their data with leakage currents and positive feedback without a refresh cycle. The basic version of new cells consists of one write port with differential write-bit-lines and one read port with differential read-bit-lines, and the improved-leakage version of new cells consists of one write port with differential write-bit-lines and one read port with a single read-bit-line. Simulation results show that the proposed cells in this work correctly operate during their read, write, and idle cycles even while considering the process variation in 22-nm technology. In the worst case, our cells have 40% lower average leakage current in comparison with conventional 6T SRAM cell without any performance degradation. Also, our cells are hardened. Thus, they have zero soft error rate.

[1]  Christos A. Papachristou,et al.  A New Asymmetric SRAM Cell to Reduce Soft Errors and Leakage Power in FPGA , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[2]  A.F. Witulski,et al.  Single Event Upsets in Deep-Submicrometer Technologies Due to Charge Sharing , 2008, IEEE Transactions on Device and Materials Reliability.

[3]  Hiroyuki Yamauchi,et al.  Embedded SRAM Design in Nanometer-Scale Technologies , 2009 .

[4]  K. Takeda,et al.  A read-static-noise-margin-free SRAM cell for low-V/sub dd/ and high-speed applications , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[5]  A.P. Chandrakasan,et al.  A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy , 2008, IEEE Journal of Solid-State Circuits.

[6]  Jason Helge Anderson,et al.  Active leakage power optimization for FPGAs , 2006, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Luigi Carro,et al.  Fault-Tolerance Techniques for SRAM-Based FPGAs (Frontiers in Electronic Testing) , 2006 .

[8]  R. Guerrieri,et al.  Low leakage techniques for FPGAs , 2006, IEEE Journal of Solid-State Circuits.

[9]  G. Srinivasan,et al.  Accurate, predictive modeling of soft error rate due to cosmic rays and chip alpha radiation , 1994, Proceedings of 1994 IEEE International Reliability Physics Symposium.

[10]  Ricardo P. Jasinski,et al.  Fault-Tolerance Techniques for SRAM-Based FPGAs , 2007, Comput. J..

[11]  Kevin Zhang.  Embedded Memories for Nano-Scale VLSIs , 2009 .

[12]  David Blaauw,et al.  Modeling and analysis of leakage power considering within-die process variations , 2002, ISLPED '02.

[13]  Mark C. Johnson,et al.  Leakage control with efficient use of transistor stacks in single threshold CMOS , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[14]  Kaushik Roy,et al.  Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Dan Alexandrescu,et al.  Low-Cost Highly-Robust Hardened Cells Using Blocking Feedback Transistors , 2008, 26th IEEE VLSI Test Symposium (vts 2008).

[16]  Masahiro Nomura,et al.  A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications , 2006, IEEE Journal of Solid-State Circuits.

[17]  S. Jahinuzzaman,et al.  A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read Capability , 2009, IEEE Transactions on Nuclear Science.

[18]  D. Rossi,et al.  Latch Susceptibility to Transient Faults and New Hardening Approach , 2007, IEEE Transactions on Computers.

[19]  Kaushik Roy,et al.  Leakage in nano-scale technologies: mechanisms, impact and design considerations , 2004, Proceedings. 41st Design Automation Conference, 2004..

[20]  Tim Tuan,et al.  Active leakage power optimization for FPGAs , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[21]  P. Oldiges,et al.  Modeling Single-Event Upsets in 65-nm Silicon-on-Insulator Semiconductor Devices , 2006, IEEE Transactions on Nuclear Science.

[22]  R. Reed,et al.  Heavy ion and proton-induced single event multiple upset , 1997 .

[23]  Dhiraj K. Pradhan,et al.  A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead , 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

[24]  K. Osada,et al.  A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme , 2005, IEEE Journal of Solid-State Circuits.

[25]  Mohammad T. Manzuri Shalmani,et al.  New configuration memory cells for FPGA in nano-scaled CMOS technology , 2011, Microelectron. J..

[26]  Massoud Pedram,et al.  Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology , 2008, IEEE Trans. Very Large Scale Integr. Syst..

[27]  P. Cheynet,et al.  Effects of radiation on digital architectures: one year results from a satellite experiment , 1999, Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387).

[28]  Kiamal Z. Pekmestzi,et al.  A New Low-Power Soft-Error Tolerant SRAM Cell , 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

[29]  Volkan Kursun,et al.  Low power and robust 7T dual-Vt SRAM circuit , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[30]  Babak Falsafi,et al.  A case for asymmetric-cell cache memories , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[31]  Andreas Moshovos,et al.  Low-leakage asymmetric-cell SRAM , 2002, ISLPED '02.

[32]  Bashir M. Al-Hashimi,et al.  Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[33]  Yong-Bin Kim,et al.  A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[34]  Pankaj Agarwal,et al.  A low leakage and SNM free SRAM cell design in deep sub micron CMOS technology , 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

[35]  M. Nicolaidis,et al.  Design for soft error mitigation , 2005, IEEE Transactions on Device and Materials Reliability.

[36]  Francis G. Wolff,et al.  Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA , 2007 .

[37]  Anna W. Topol,et al.  Stable SRAM cell design for the 32 nm node and beyond , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[38]  Robert C. Aitken,et al.  Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS , 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

[39]  Donald J. Patterson,et al.  Computer organization and design: the hardware-software interface (appendix a , 1993 .

[40]  T. Calin,et al.  Upset hardened memory design for submicron CMOS technology , 1996 .

[41]  H. Toyoshima,et al.  A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro , 2000, IEEE Journal of Solid-State Circuits.