Power optimization of 8b/10b encoder decoder used for high speed communication

In this paper an 8B/10B encoder and 10B/8B decoder is implemented which are widely used in high speed applications. In this paper we have used NAND/NOR gate instead of AND/OR gate used in earlier work. We calculated on-chip and hierarchy power for two frequencies (i.e. 20 MHz and 200 MHz) for both encoder and decoder using AND/OR gate and encoder and decoder using NAND/NOR gate. Using NAND/NOR gate we can able to reduce the power consumption of the encoder and decoder. For 20 MHz frequency, on-chip power and hierarchy power of encoder is reduced by 1.8% and 60% respectively and on-chip power and hierarchy power of decoder is reduced by 0% and 60%. For 200 MHz on-chip power and hierarchy power of encoder is reduced by 16.7% and 56.56% respectively and on-chip power and hierarchy power of decoder is reduced by 2.59% and 63.26% respectively. Both the encoder and decoder were implemented using verilog HDL in ModelSim 10.3 and for calculating power we used Xpower Analyzer of Xilinx 13.4.