Optimization and Comparison of Synchronizers

Bisection with restarts [1] provides a way to quantify the failure probabilities of real-world synchronizer circuits. More recently [2] showed how time-varying, linear dynamics can be derived for non-linear synchronizer circuits building upon the bisection with restarts method. Here, we show that this linear model can be decomposed into component-wise contributions to synchronizer performance. This enables automatic optimization of device sizing to minimize the probability of failure. Furthermore, we can compare existing designs, optimizing each circuit to provide a fair comparison. The component-wise analysis explains the differences between designs by showing how each device contributes to metastability resolution over the time allotted for synchronization.