Charge-based computing with analogue reconfigurable gates

As the world enters the age of ubiquitous computing, the need for reconfigurable hardware operating close to the fundamental limits of energy consumption becomes increasingly pressing. Simultaneously, scaling-driven performance improvements within the framework of traditional analogue and digital design become progressively more restricted by fundamental physical constraints. Thus, a true paradigm shift in electronics design is required for fuelling the next big burst in technology. Here we lay the foundations of a new design paradigm that fuses analogue and digital thinking by combining digital electronics with memristive devices for achieving charge-based computation; information processing where every dissipated charge counts. This is realised by introducing memristive devices into standard logic gates, thus rendering them reconfigurable and able to perform analogue computation at a power cost close to digital. The power of this concept is then showcased by experimentally demonstrating a hardware data clusterer and a fuzzy NAND gate using this principle.

[1]  R. Jacob Baker,et al.  CMOS Circuit Design, Layout, and Simulation , 1997 .

[2]  J Joshua Yang,et al.  Memristive devices for computing. , 2013, Nature nanotechnology.

[3]  Farnood Merrikh-Bayat,et al.  Training and operation of an integrated neuromorphic network based on metal-oxide memristors , 2014, Nature.

[4]  Sally A. McKee,et al.  Hitting the memory wall: implications of the obvious , 1995, CARN.

[5]  L. Chua Memristor-The missing circuit element , 1971 .

[6]  Gert Cauwenberghs,et al.  Neuromorphic Silicon Neuron Circuits , 2011, Front. Neurosci.

[7]  Ali Khiat,et al.  Unsupervised learning in probabilistic neural networks with multi-state metal-oxide memristive synapses , 2016, Nature Communications.

[8]  Ali Khiat,et al.  Real-time encoding and compression of neuronal spikes by metal-oxide memristors , 2016, Nature Communications.

[9]  Subhasish Mitra,et al.  Three-dimensional integration of nanotechnologies for computing and data storage on a single chip , 2017, Nature.

[10]  Andrea Zanella,et al.  EC-CENTRIC: An Energy- and Context-Centric Perspective on IoT Systems and Protocol Design , 2017, IEEE Access.

[11]  Rodrigo Quian Quiroga,et al.  Past, present and future of spike sorting techniques , 2015, Brain Research Bulletin.

[12]  T. Prodromakis,et al.  High Density Crossbar Arrays with Sub- 15 nm Single Cells via Liftoff Process Only , 2016, Scientific Reports.

[13]  Andrew Jackson,et al.  Minimum requirements for accurate and efficient real-time on-chip spike sorting , 2014, Journal of Neuroscience Methods.

[14]  R. Waser,et al.  Nanoionics-based resistive switching memories. , 2007, Nature materials.

[15]  R. Williams,et al.  Sub-nanosecond switching of a tantalum oxide memristor , 2011, Nanotechnology.

[16]  R. Quian Quiroga,et al.  Unsupervised Spike Detection and Sorting with Wavelets and Superparamagnetic Clustering , 2004, Neural Computation.

[17]  G.E. Moore,et al.  Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.

[18]  Qiangfei Xia,et al.  Self-aligned memristor cross-point arrays fabricated with one nanoimprint lithography step. , 2010, Nano letters.

[19]  Spyros Stathopoulos,et al.  Multibit memory operation of metal-oxide bi-layer memristors , 2017, Scientific Reports.

[20]  Wei D. Lu,et al.  Sparse coding with memristor networks. , 2017, Nature nanotechnology.