论文信息 - Design and performance evaluation of a systolic architecture for hidden-surface removal

Design and performance evaluation of a systolic architecture for hidden-surface removal

In this paper, we propose a systolic architecture for hidden-surface removal. Systolic architecture is a kind of parallel architecture best known for its easy VLSI implementability. After discussing the design details of the architecture, we present the results of the simulation experiments conducted in order to evaluate the performance of the architecture.

Lalit M. Patnaik | Venkatramana G. Ajjanagadde

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