A practical design method for prototyping self-timed processors using FPGAs

This paper describes a practical design method for protoyping self-timed processors using FPGAs. It adresses shortcomings of typical implementation strategies that use floorplanning to compensate for the lack of support of asynchronous designs in conventional FPGA tools. It is shown that a reported self-timed design technique can be used with a proposed set of constraints to make it fully compliant with standard timing analysis engines. This results in a more effective implementation strategy that makes FPGAs convenient for verifiying self-timed processor designs. The design technique and the timing-driven implementation method are validated by protoyping an 8-bit processor that achieves 11.1 MIPS performance while computing the Fibonacci sequence.

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