A direct digital period synthesis circuit

This paper presents a direct digital period synthesis (DDPS) circuit, which combines the DDS' ability to control the frequency, with the speed and accuracy of a delay-locked-loop-based frequency multiplier. The resulting DDPS circuit can synthesize clocks with accurately controlled periods. It can do clean and accurate transitions from a first target period to a second target period, both periods having precisely specified durations. A prototype integrated circuit reported in this paper, implemented in 0.25 /spl mu/m CMOS technology, synthesizes clocks with frequencies up to 500 MHz and peak-to-peak jitter measured at 208 ps.

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