Physical design tradeoffs in power distribution networks for 3-D ICs

A physical model for the design of the power distribution networks in three-dimensional integrated circuits is proposed. The tradeoffs among the different design parameters are specified and analyzed. Different case studies are explored, indicating that smaller and denser TSVs can deliver power more efficiently as compared to larger and coarsely distributed TSVs. The interplay between the TSV count and the intra-plane power distribution network in reducing the power supply noise is also shown.

[1]  Eby G. Friedman,et al.  Power Distribution Networks with On-Chip Decoupling Capacitors , 2007 .

[2]  Soha Hassoun,et al.  System-level comparison of power delivery design for 2D and 3D ICs , 2009, 2009 IEEE International Conference on 3D System Integration.

[3]  Chung-Kuan Cheng,et al.  3D power distribution network co-design for nanoscale stacked silicon ICs , 2008, 2008 IEEE-EPEP Electrical Performance of Electronic Packaging.

[4]  W. S. Song,et al.  Power distribution techniques for VLSI circuits , 1986 .

[5]  Robert S. Patti,et al.  Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs , 2006, Proceedings of the IEEE.

[6]  Gang Huang,et al.  Power Delivery for 3D Chip Stacks: Physical Modeling and Design Implication , 2007, 2007 IEEE Electrical Performance of Electronic Packaging.

[7]  W. Dehaene,et al.  Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs , 2010, IEEE Transactions on Electron Devices.

[8]  Eli Chiprout Fast flip-chip power grid analysis via locality and grid shells , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[9]  Pingqiang Zhou,et al.  Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors , 2009, 2009 Asia and South Pacific Design Automation Conference.