A Short Survey at the Intersection of Reliability and Security in Processor Architecture Designs

Over the next decade, processor design will encounter a number of challenges. The ongoing miniaturization of semiconductor manufacturing technologies that has enabled the integration of hundreds to thousands of processing cores on a single chip is pushing the limits of physical laws. The fabrication process has also grown more complex and globalized with widespread use of third-party IPs (intellectual properties). This development ecosystem has complicated the security and trust view of processors. Some of the pressing processor architecture design questions are: (1) how to use reconfiguration and redundancy to improve reliability without introducing additional and potentially insecure system states, (2) what analytical models lend themselves best to the joint implementation of reliability and security in these systems, and (3) how to optimally and securely share resources and data among processing elements with high degree of reliability. In this work, we present and discuss (1) principal reliability approaches - error correction code, modular redundancy, (2) processor architecture specific reliability, (3) major secure processor architectures. We also highlight key features of a small representative class of the secure and reliable architectures.

[1]  J. Johnson,et al.  Using Duplication with Compare for On-line Error Detection in FPGA-based Designs , 2008, 2008 IEEE Aerospace Conference.

[2]  Bing-Fei Wu,et al.  Simple error detection methods for hardware implementation of Advanced Encryption Standard , 2006, IEEE Transactions on Computers.

[3]  Israel Koren,et al.  Incorporating error detection and online reconfiguration into a regular architecture for the advanced encryption standard , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

[4]  Joel Emer,et al.  A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[5]  Amir Salman Avestimehr,et al.  Coded Computation Over Heterogeneous Clusters , 2019, IEEE Transactions on Information Theory.

[6]  G. Edward Suh,et al.  Aegis: A Single-Chip Secure Processor , 2007, IEEE Des. Test Comput..

[7]  Joel S. Emer,et al.  The soft error problem: an architectural perspective , 2005, 11th International Symposium on High-Performance Computer Architecture.

[8]  Zhiguo Ding,et al.  Nonorthogonal Multiple Access for 5G , 2018, 5G Networks: Fundamental Requirements, Enabling Technologies, and Operations Management.

[9]  Israel Koren,et al.  A parity code based fault detection for an implementation of the Advanced Encryption Standard , 2002, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings..

[10]  G. Edward Suh,et al.  AEGIS: architecture for tamper-evident and tamper-resistant processing , 2003 .

[11]  G. Edward Suh,et al.  Design and implementation of the AEGIS single-chip secure processor using physical random functions , 2005, 32nd International Symposium on Computer Architecture (ISCA'05).

[12]  Mihailo Isakov,et al.  Hermes: Secure heterogeneous multicore architecture design , 2017, 2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

[13]  Intel ® Trusted Execution Technology ( Intel ® TXT ) , .

[14]  N. Okumura,et al.  Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications , 2009, IEEE Journal of Solid-State Circuits.

[15]  Adrian Evans,et al.  A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Codes , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[16]  Wei Hwang,et al.  Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip , 2008, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008).

[17]  Dimitris S. Papailiopoulos,et al.  Speeding up distributed machine learning using codes , 2016, ISIT.

[18]  iOS Security , 2013 .

[19]  Sanjay J. Patel,et al.  Characterizing the effects of transient faults on a high-performance processor pipeline , 2004, International Conference on Dependable Systems and Networks, 2004.

[20]  Rafal Wojtczuk,et al.  Another Way to Circumvent Intel ® Trusted Execution Technology , 2009 .

[21]  Nihad Hadzic,et al.  IBM 4765 cryptographic coprocessor , 2012, IBM J. Res. Dev..