On the evaluation of arbitrary defect coverage of test sets

Efficient methods to evaluate the quality of a test set in terms of its coverage of arbitrary defects in a circuit are presented. Our techniques rapidly estimate arbitrary defect coverage because they are independent of specific, physical, fault models. We overcome the potentially explosive computational requirements associated with considering all possible defects by implicitly evaluating multiple faults (of all types) simultaneously and by exploiting the local nature of defects. Our experiments show that a strong correlation exists between stuck-at fault coverage and defects whose behavior is independent of the input vectors. Our techniques are capable of identifying regions in the circuit where defects may escape the test set. We also demonstrate how the chances of detection of an arbitrary defect by a test set vary when a single stuck-at-fault within the vicinity of that defect is detected multiple times by the test set.

[1]  F. Joel Ferguson,et al.  Carafe: an inductive fault analysis tool for CMOS VLSI circuits , 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.

[2]  Edward J. McCluskey,et al.  Analysis of pattern-dependent and timing-dependent failures in an experimental test chip , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[3]  Sheldon B. Akers,et al.  Universal Test Sets for Logic Networks , 1972, IEEE Transactions on Computers.

[4]  Irith Pomeranz,et al.  On the effects of test compaction on defect coverage , 1996, Proceedings of 14th VLSI Test Symposium.

[5]  Irith Pomeranz,et al.  Stuck-at tuple-detection: a fault model based on stuck-at faults for improved defect coverage , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

[6]  Melvin A. Breuer,et al.  Digital Systems Testing and Design for Testability , 1990 .

[7]  Robert C. Aitken,et al.  THE EFFECT OF DIFFERENT TEST SETS ON QUALITY LEVEL PREDICTION: WHEN IS 80% BETTER THAN 90%? , 1991, 1991, Proceedings. International Test Conference.

[8]  Janak H. Patel,et al.  HITEC: a test generation package for sequential circuits , 1991, Proceedings of the European Conference on Design Automation..

[9]  M. Ray Mercer,et al.  On the decline of testing efficiency as fault coverage approaches 100% , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[10]  Edward J. McCluskey,et al.  An experimental chip to evaluate test techniques experiment results , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[11]  Rodolfo Betancourt.  Derivation of Minimum Test Sets for Unate Logical Circuits , 1971, IEEE Transactions on Computers.

[12]  John P. Hayes,et al.  High-coverage ATPG for datapath circuits with unimplemented blocks , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[13]  Masahiro Fujita,et al.  Modeling the unknown! Towards model-independent fault and error diagnosis , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).