论文信息 - VLSI Implementation of Inverse Discrete for MPEG2 HDTV Video Decoding Cosine Transformer and Motion Compensator

VLSI Implementation of Inverse Discrete for MPEG2 HDTV Video Decoding Cosine Transformer and Motion Compensator

An MPEG2 video decoder core dedicated to MP@HL (Main Profile at High LRvel) images is described with the main theme focused on an inverse discrete cosine transformer and a motion compensator. By means of various novel architectures, the inverse discrete cosine transformer achieves a high throughput, and the motion compensator performs different types of picture prediction modes employed by the MPEG2 algorithm. The decoder core, implemented in the total chip area of 22.0 mm2 by a 0.6-pm triple-metal CMOS technology, processes a macroblock within 3.84 ps, and therefore is capable of decoding HDTV (1920 x 1152 pels) images in real time.

Takao Onoye | Toshihiro Masaki | Isao Shirakawa | Yasuo Morimoto

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