Software transformations for sequential test generation

This paper presents software (model) transformations that can be used to effectively generate high fault coverage test sets. Unlike synthesis or design for testability methods which involve hardware modifications, this approach does not modify the hardware design. Instead, it transforms a software model of the design into a new software model that has desirable testability properties. A sequential test generator generates tests for the new model. The new model may not be functionally equivalent to the original design but our transformations guarantee that the tests generated for the new model can always be inverse mapped to serve as tests for the original design. Experimental results show that significantly high fault coverage can be achieved by using this approach.

[1]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[2]  Srimat T. Chakradhar,et al.  Sequential circuits with combinational test generation complexity , 1996, Proceedings of 9th International Conference on VLSI Design.

[3]  Ronald L. Rivest,et al.  Introduction to Algorithms , 1990 .

[4]  Robert K. Brayton,et al.  Retiming and resynthesis: optimizing sequential networks with combinational techniques , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Srimat T. Chakradhar,et al.  Optimum retiming of large sequential circuits , 1995, Proceedings of the 8th International Conference on VLSI Design.

[6]  Janusz Rajski,et al.  On Test Set Preservation of Retimed Circuits , 1995, 32nd Design Automation Conference.

[7]  Robert K. Brayton,et al.  The Validity of Retiming Sequential Circuits , 1995, 32nd Design Automation Conference.

[8]  Miodrag Potkonjak,et al.  Sequential Circuit Delay Optimization Using Global Path Delays , 1993, 30th ACM/IEEE Design Automation Conference.

[9]  Vishwani D. Agrawal,et al.  An exact algorithm for selecting partial scan flip-flops , 1995, J. Electron. Test..

[10]  Xinghao Chen,et al.  Dynamic state and objective learning for sequential circuit automatic test generation using recomposition equivalence , 1994, Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing.

[11]  Janusz Rajski,et al.  Complexity of sequential ATPG , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[12]  Srimat T. Chakradhar,et al.  Retiming with logic duplication transformation: theory and an application to partial scan , 1996, Proceedings of 9th International Conference on VLSI Design.

[13]  Robert K. Brayton,et al.  Sequential circuit design using synthesis and optimization , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[14]  Janak H. Patel,et al.  HITEC: a test generation package for sequential circuits , 1991, Proceedings of the European Conference on Design Automation..