Systolic array simulation for quantification of speed/area parameters

A comprehensive circuit simulation of a VLSI (Very Large Scale Integration) systolic array processor for band matrix triangula tion is developed. A systolic array structure is composed of sim ple, regularly connected processing elements configured to rap idly triangulate large, band form, linear equation systems. I/O circuit models are developed which provide operand demulti plexinglmultiplexing necessary to convert serial operand I/O, at the chip boundaries, to a parallel broadcasting of operands to/from the processing cells. The complete layout of the model is a tessellated design of pro cessing elements and I/O modules which ideally will be fabri cated on a single chip. Fundamental design parameters which may be manipulated in the simulation include a scalable litho graphic linewidth, the number of bits per word and matrix bandwidth. Comparisons are made of total propagation delay time and chip size versus matrix bandwidth. These results, in turn, lead to an assessment of the feasibility and advantages of this type of special- purpose VLSI computing structure.