A Two-Stage Fully Differential Inverter-Based Self-Biased CMOS Amplifier With High Efficiency

A two-stage fully differential CMOS amplifier comprising inverters as input structures and employing self-biasing techniques is presented. The proposed amplifier benefits from an optimum compensation through time-domain optimization which permits achieving high energy efficiency. Moreover, it achieves the highest efficiency of its class and although it relies on a quasi-class-A topology, it is comparable to class-AB amplifiers. Detailed circuit analyses such as differential-mode, common-mode feedback, noise, slew rate, and input/output range are carried out. Based on these analyses, a manual design methodology and a genetic algorithm based optimization are presented. Finally, the most relevant experimental results for an integrated circuit prototype designed in a 0.13 μm 1.2 V standard CMOS technology are shown.

[1]  Willy Sansen,et al.  A CMOS large-swing low-distortion three-stage class AB power amplifier , 1990 .

[2]  Gabor C. Temes,et al.  Design-oriented estimation of thermal noise in switched-capacitor circuits , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[3]  M. Figueiredo,et al.  Two-stage fully-differential inverter-based self-biased CMOS amplifier with high efficiency , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[4]  R.W. Brodersen,et al.  Design of a Sub-mW 960-MHz UWB CMOS LNA , 2006, IEEE Journal of Solid-State Circuits.

[5]  K. Yeo,et al.  Effect of technology scaling on the 1/f noise of deep submicron PMOS transistors , 2004 .

[6]  W. Sansen.  Challenges in analog IC design submicron CMOS technologies , 1996, 1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings.

[7]  Willy Sansen,et al.  Class AB CMOS amplifiers with high efficiency , 1990 .

[8]  Nuno Paulino,et al.  Optimization of multi-stage amplifiers in deep-submicron CMOS using a distributed/parallel genetic algorithm , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[9]  Gianluca Giustolisi,et al.  High-Drive and Linear CMOS Class-AB Pseudo-Differential Amplifier , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[10]  L. R. Carley,et al.  Analysis of switched-capacitor common-mode feedback circuit , 2003, IEEE Trans. Circuits Syst. II Express Briefs.

[11]  Mohammad M. Ahmadi,et al.  A new modeling and optimization of gain-boosted cascode amplifier for high-speed and low-voltage applications , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[12]  Willy Sansen,et al.  analog design essentials , 2011 .

[13]  Franco Maloberti,et al.  Slew-rate and gain enhancement in two stage operational amplifiers , 2009, 2009 IEEE International Symposium on Circuits and Systems.

[14]  Pradip Mandal,et al.  A self-biased high performance folded cascode CMOS op-amp , 1997, Proceedings Tenth International Conference on VLSI Design.

[15]  L. Ratti,et al.  Noise Characterization of 130 nm and 90 nm CMOS Technologies for Analog Front-end Electronics , 2006, 2006 IEEE Nuclear Science Symposium Conference Record.

[16]  Johan H. Huijsing,et al.  A 100-MHz 100-dB operational amplifier with multipath nested Miller compensation structure , 1992 .

[17]  Omid Shoaei,et al.  Very low-voltage, low-power and fast-settling OTA for switched-capacitor applications , 2002, The 14th International Conference on Microelectronics,.

[18]  B.K. Ahuja,et al.  An improved frequency compensation technique for CMOS operational amplifiers , 1983, IEEE Journal of Solid-State Circuits.

[19]  Georges Gielen,et al.  A behavioral signal path modeling methodology for qualitative insight in and efficient sizing of CMOS opamps , 1997, ICCAD 1997.

[20]  Ali Hajimiri,et al.  Generalized Time- and Transfer-Constant Circuit Analysis , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[21]  Mel Bazes,et al.  Two novel fully complementary self-biased CMOS differential amplifiers , 1991 .

[22]  Willy Sansen,et al.  Feedforward compensation techniques for high-frequency CMOS amplifiers , 1990 .

[23]  Gaetano Palumbo,et al.  Advances in Reversed Nested Miller Compensation , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[24]  Alfio Dario Grasso,et al.  Comparison of the Frequency Compensation Techniques for CMOS Two-Stage Miller OTAs , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

[25]  José Silva-Martínez,et al.  The Recycling Folded Cascode: A General Enhancement of the Folded Cascode Amplifier , 2009, IEEE Journal of Solid-State Circuits.

[26]  Shen-Iuan Liu,et al.  A one-wire approach for skew-compensating clock distribution based on bidirectional techniques , 2001 .

[27]  Hoda S. Abdel-Aty-Zohdy,et al.  Compact High Gain CMOS Op Amp Design using Comparators , 1999 .

[28]  Ka Nang Leung,et al.  Analysis of multistage amplifier-frequency compensation , 2001 .

[29]  Wenhua Yang,et al.  A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input , 2001, IEEE J. Solid State Circuits.

[30]  Ramón González Carvajal,et al.  Power efficient fully differential low-voltage two stage class AB/AB op-amp architectures , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[31]  Boris Murmann,et al.  The Design of Fast-Settling Three-Stage Amplifiers Using the Open-Loop Damping Factor as a Design Parameter , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.