A pipeline A/D converter for WCDMA applications

A 40 MS/s 8-bit CMOS pipeline A/D converter for Wideband CDMA (WCDMA) applications is implemented in a 0.5 /spl mu/m CMOS technology. Small power consumption is achieved by using 1.5 bit/stage pipeline architecture and by scaling the capacitor values along the converter. Digital correction allows us also to use dynamic comparators. The multiplying D/A converters (MDACs) utilize a modified folded cascode amplifier. The measured DNL is 0.85 LSB and INL 1.91 LSB. The converter achieves over 48 dBc SFDR and more than 41 dBc SNDR dissipating 61 mW from a 2.7 V supply.

[1]  J. Ryynanen,et al.  A wide-band direct conversion receiver for WCDMA applications , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[2]  Jussi Ryynanen,et al.  A 2-GHz wide-band direct conversion receiver for WCDMA applications , 1999, IEEE J. Solid State Circuits.

[3]  S. H. Lewis,et al.  A pipelined 5-Msample/s 9-bit analog-to-digital converter , 1987 .

[4]  Geir S. Østrem,et al.  A Compact 3V, 70mW, 12-bit Video-Speed CMOS ADC , 1998 .

[5]  Paul R. Gray,et al.  A 10 b, 20 Msample/s, 35 mW pipeline A/D converter , 1995, IEEE J. Solid State Circuits.

[6]  Bruce E. Peetz.  Dynamic Testing of Waveform Recorders , 1983, IEEE Transactions on Instrumentation and Measurement.