A Comprehensive Fault Injection Strategy for Embedded Systems Reliability Assessment

The embedded systems industry is moving towards the integration of higher performance, yet less reliable electronic components into new product generations. Technology and voltage scaling increased dramatically the susceptibility of new devices not only to Single Bit Upsets (SBU), but also to Multiple Bit Upsets (MBU). However, the system reliability assessment at the design phase of fault-tolerant computer systems is a complex and critical task. In this context, it is mandatory to enhance reliability analysis and evaluation techniques at early-stage of the system development. In this paper, we present a technique for reliability evaluation of embedded systems at early-stage by taking into account the application behavior and SBU/MBU phenomena. Instead of using the random fault injection, our approach models the architecture behavior under real working conditions. Our results demonstrate the efficiency of the proposed fault injection simulation platform for early-stage reliability studies.

[1]  Fernando Henrique Ataíde,et al.  AUTomotive Open System Architecture - concepts, benefits and challenges , 2007 .

[2]  Alberto Bosio,et al.  Software testing and software fault injection , 2015, 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

[3]  Tânia Basso,et al.  J-SWFIT: A Java Software Fault Injection Tool , 2011, 2011 5th Latin-American Symposium on Dependable Computing.

[4]  Alan Wood,et al.  The impact of new technology on soft error rates , 2011, 2011 International Reliability Physics Symposium.

[5]  Mehdi Baradaran Tahoori,et al.  Layout-Based Modeling and Mitigation of Multiple Event Transients , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Giorgio Di Natale,et al.  A survey on simulation-based fault injection tools for complex systems , 2014, 2014 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

[7]  Benjamin Vedder,et al.  Testing Safety-Critical Systems using Fault Injection and Property-Based Testing , 2015 .

[8]  H. Kawaguchi,et al.  Bit error rate estimation in SRAM considering temperature fluctuation , 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

[9]  Dakai Zhu,et al.  Reliability-Aware Energy Management for Periodic Real-Time Tasks , 2009, IEEE Trans. Computers.

[10]  Eric Cheng,et al.  CLEAR: Cross-layer exploration for architecting resilience: Combining hardware and software techniques to tolerate soft errors in processor cores , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[11]  Alois Knoll,et al.  A framework for reliability-aware design exploration on MPSoC based systems , 2012, Design Automation for Embedded Systems.

[12]  Alessandro Paccagnella,et al.  Temperature dependence of neutron-induced soft errors in SRAMs , 2012, Microelectron. Reliab..

[13]  H. Puchner,et al.  Investigation of multi-bit upsets in a 150 nm technology SRAM device , 2005, IEEE Transactions on Nuclear Science.

[14]  Jacob A. Abraham,et al.  FERRARI: A Flexible Software-Based Fault and Error Injection System , 1995, IEEE Trans. Computers.

[15]  Trevor Mudge,et al.  MiBench: A free, commercially representative embedded benchmark suite , 2001 .

[16]  Donald E. Thomas,et al.  A case for lifetime-aware task mapping in embedded chip multiprocessors , 2010, 2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[17]  Jesse H. Poore,et al.  Statistical testing of software based on a usage model , 1995, Softw. Pract. Exp..

[18]  Hamid R. Zarandi,et al.  Susceptibility Analysis of LEON3 Embedded Processor against Multiple Event Transients and Upsets , 2012, 2012 IEEE 15th International Conference on Computational Science and Engineering.