Dynamic minimization of OKFDDs
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[1] Beate Bollig,et al. Improving the Variable Ordering of OBDDs Is NP-Complete , 1996, IEEE Trans. Computers.
[2] Marek A. Perkowski,et al. Free Kronecker decision diagrams and their application to Atmel 6000 series FPGA mapping , 1994, EURO-DAC '94.
[3] R. Rudell. Dynamic variable ordering for ordered binary decision diagrams , 1993, ICCAD 1993.
[4] Rolf Drechsler,et al. On the Relation Betwen BDDs and FDDs , 1995, LATIN.
[5] Rolf Drechsler,et al. Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.
[6] Bernd Becker,et al. A BDD-based algorithm for computation of exact fault detection probabilities , 1993, FTCS-23 The Twenty-Third International Symposium on Fault-Tolerant Computing.
[7] Wolfgang Rosenstiel,et al. FDD based technology mapping for FPGA , 1992, Proceedings Euro ASIC '92.
[8] R. Rudell. Dynamic variable ordering for ordered binary decision diagrams , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).
[9] Malgorzata Marek-Sadowska,et al. Detecting Symmetric Variables in Boolean Functions using Generalized Reel-Muller Forms , 1994, ISCAS.
[10] Wolfgang Rosenstiel,et al. Multilevel logic synthesis based on functional decision diagrams , 1992, [1992] Proceedings The European Conference on Design Automation.
[11] Kenneth J. Supowit,et al. Finding the Optimal Variable Ordering for Binary Decision Diagrams , 1987, 24th ACM/IEEE Design Automation Conference.
[12] Masahiro Fujita,et al. On variable ordering of binary decision diagrams for the application of multi-level logic synthesis , 1991, Proceedings of the European Conference on Design Automation..
[13] Rolf Drechsler,et al. Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams , 1994, 31st Design Automation Conference.
[14] Randal E. Bryant,et al. Symbolic Boolean manipulation with ordered binary-decision diagrams , 1992, CSUR.
[15] Malgorzata Marek-Sadowska,et al. Boolean Matching Using Generalized Reed-Muller Forms , 1994, 31st Design Automation Conference.
[16] Randal E. Bryant,et al. Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.
[17] Bernd Becker,et al. Fast OFDD based minimization of fixed polarity Reed-Muller expressions , 1994, EURO-DAC '94.
[18] Randal E. Bryant,et al. On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication , 1991, IEEE Trans. Computers.
[19] R. Drechsler,et al. On variable ordering and decomposition type choice in OKFDDs , 1995, Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair.
[20] Tsutomu Sasao,et al. Logic Synthesis and Optimization , 1997 .
[21] F. Somenzi,et al. Who are the variables in your neighbourhood , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).
[22] Rolf Drechsler,et al. On the Relation between BDDs and FDDs , 1995, Inf. Comput..
[23] Marek A. Perkowski,et al. Free Kronecker Decision Diagrams and their Application to Atmel 6000 FPGA Mapping , 1995 .
[24] F. Brglez,et al. A neutral netlists of 10 combinational circuits and a target translator in FORTRAN , 1985 .
[25] Rolf Drechsler,et al. OKFDDs versus OBDDs and OFDDs , 1995, ICALP.
[26] Seh-Woong Jeong,et al. Extended BDD's: trading off canonicity for structure in verification algorithms , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.
[27] Albert R. Wang,et al. Logic verification using binary decision diagrams in a logic synthesis environment , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.
[28] Hiroshi Sawada,et al. Minimization of binary decision diagrams based on exchanges of variables , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.
[29] Shin-ichi Minato,et al. Zero-Suppressed BDDs for Set Manipulation in Combinatorial Problems , 1993, 30th ACM/IEEE Design Automation Conference.
[30] Chikahiro Hori,et al. Interleaving based variable ordering methods for ordered binary decision diagrams , 1993, ICCAD.
[31] Hiroshige Fujii,et al. Interleaving based variable ordering methods for ordered binary decision diagrams , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).