A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS

An 18-Mb full ternary CAM with low-voltage matchline sensing scheme (LVMLSS) is designed and fabricated in 65-nm bulk CMOS process. LVMLSS has three key techniques: voltage down converter, differential sense amplifier with matchline isolation, and reference voltage generation scheme. With these techniques, LVMLSS can reduce the dynamic power consumption of matchlines to 33% compared with conventional one and realizes 42% fast match-line sensing. At 1.0-V typical supply voltage, 250-MHz search frequency is achieved. The power consumption of fully paralleled search operation at 250 MHz is 9.3 W, which is 66% smaller than previous work. This work has realized high-speed, low-power, and robust large-scale TCAM. We believe that this work will greatly contribute to reducing the power of network systems.

[1]  Y. Matsuda,et al.  A charge recycling TCAM with Checkerboard Array arrangement for low power applications , 2008, 2008 IEEE Asian Solid-State Circuits Conference.

[2]  K. J. Schultz,et al.  Fully Parallel 30-MHz , 2 . 5-Mb CAM , 1998 .

[3]  A. Roth,et al.  Advanced ternary CAM circuits on 0.13 /spl mu/m logic process technology , 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

[4]  G. Kasai,et al.  200MHz/200MSPS 3.2W at 1.5V Vdd, 9.4Mbits ternary CAM with new charge injection match detect circuits and bank selection scheme , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[5]  K. Pagiamtzis,et al.  Content-addressable memory (CAM) circuits and architectures: a tutorial and survey , 2006, IEEE Journal of Solid-State Circuits.

[6]  Hong-Seok Kim,et al.  66 MHz 2.3 M ternary dynamic content addressable memory , 2000, Records of the IEEE International Workshop on Memory Technology, Design and Testing.

[7]  J. Miyake,et al.  An 8-kbit content-addressable and reentrant memory , 1985, IEEE Journal of Solid-State Circuits.

[8]  K. Fujishima,et al.  A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture , 2005, IEEE Journal of Solid-State Circuits.

[9]  Igor Arsovski,et al.  A 32 nm 0.58-fJ/Bit/Search 1-GHz Ternary Content Addressable Memory Compiler Using Silicon-Aware Early-Predict Late-Correct Sensing With Embedded Deep-Trench Capacitor Noise Mitigation , 2013, IEEE Journal of Solid-State Circuits.

[10]  Toshifumi Kobayashi,et al.  A 288-kbit fully parallel content addressable memory using stacked capacitor cell structure , 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

[11]  T. Ogura,et al.  A 336-kbit content addressable memory for highly parallel image processing , 1996, Proceedings of Custom Integrated Circuits Conference.

[12]  Toshifumi Kobayashi,et al.  A 288-kb fully parallel content addressable memory using a stacked-capacitor cell structure , 1992 .

[13]  Wei Hwang,et al.  A 65 nm 0.165 fJ/Bit/Search 256 $\,\times\,$144 TCAM Macro Design for IPv6 Lookup Tables , 2011, IEEE Journal of Solid-State Circuits.

[14]  Ali Sheikholeslami,et al.  A mismatch-dependent power allocation technique for match-line sensing in content-addressable memories , 2003 .

[15]  R. Gibson,et al.  Fully-parallel 25 MHz 2.5 Mb CAM , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[16]  Byung-Do Yang,et al.  A Low Power Content Addressable Memory Using Low Swing Search Lines , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.