Runtime Variability Monitor for Data Retention Characteristics of Commercial NAND Flash Memory

With the scaling of flash memory cells, long-term data retention has become one of the important reliability constraints. For ensuring long-term data integrity, the storage controller employs several smart memory management techniques such as error correction code (ECC), optimal read and data refresh. However, the controller algorithm will be enhanced if the page-to-page variability within the NAND memory chip can be predicted. In this paper, we investigate the variability of data retention characteristics within a given memory chip in terms of bit error rate after high temperature bake. We find that there are a significant page-to-page and block-to-block variability on a fresh MLC memory chip. In addition, we show a method to predict the variability based on run-time characterization of the memory array.

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