Temperature-Dependent Characteristics of Cylindrical Gate-All-Around Twin Silicon Nanowire MOSFETs (TSNWFETs)

The characteristics of cylindrical gate-all-around twin silicon nanowire field-effect transistors with a radius of 5 nm have been measured in temperatures T ranging from 4 to 300 K. The dependence of the off-current suggests that thermal generation in the channel is the main leakage mechanism. The dependence of the subthreshold swing exhibits no body effects but shows degradations due to slight differences in the threshold voltages and in the body effect constants of the twin nanowires. The T dependence of the peak normalized transconductance gm /VDS gives a clue of 1-D phonon scattering and suggests that surface roughness scattering at the nanowire wall is dominant at low values.

[1]  Green-function approach to transport through a gate-surrounded Si nanowire with impurity scattering , 2007, 0706.2927.

[2]  Avik W. Ghosh,et al.  Theoretical investigation of surface roughness scattering in silicon nanowire transistors , 2005, cond-mat/0502538.

[3]  B. Ryu,et al.  High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[4]  David K. Ferry,et al.  Phonon-assisted ballistic to diffusive crossover in silicon nanowire transistors , 2005 .

[5]  Denis Flandre Silicon-on-insulator technology for high temperature metal oxide semiconductor devices and circuits , 1995 .

[6]  D. Flandre,et al.  Peculiarities of the temperature behavior of SOI MOSFETs in the deep submicron area , 2003, 2003 IEEE International Conference on SOI.

[7]  B. Ryu,et al.  Observation of Single Electron Tunneling and Ballistic Transport in Twin Silicon Nanowire MOSFETs (TSNWFETs) Fabricated by Top-Down CMOS Process , 2006, 2006 International Electron Devices Meeting.

[8]  S.C. Rustagi,et al.  Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance , 2006, 2006 International Electron Devices Meeting.

[9]  K. Ng,et al.  The Physics of Semiconductor Devices , 2019, Springer Proceedings in Physics.

[10]  B. Ryu,et al.  Gate-All-Around (GAA) Twin Silicon Nanowire MOSFET (TSNWFET) with 15 nm Length Gate and 4 nm Radius Nanowires , 2006, 2006 International Electron Devices Meeting.

[11]  G. Knoblinger,et al.  Temperature effects on trigate SOI MOSFETs , 2006, IEEE Electron Device Letters.