论文信息 - Exploring configurations of functional units in an out-of-order superscalar processor

Exploring configurations of functional units in an out-of-order superscalar processor

This study has been carried our in order to determine cost-effective configurations of functional units for multiple-issue out-of-order superscalar processors. The trace-driven simulations were performed on the six integer and the fourteen floating-point programs from the SPEC 92 suite. We first evaluate the number of instructions allowed to be concurrently processed by the execution stages of the pipeline. We then apply some restrictions on the execution issue of different instruction classes in order to define these configurations. We conclude that five to nine functional units are necessary to exploit instruction-level parallelism. An important point is that several data cache ports are required in a processor of degree 4 or more. Finally, we report on complementary results on the utilization rate of the functional units.

[1] R. M. Tomasulo,et al. An efficient algorithm for exploiting multiple arithmetic units , 1995 .

[2] Peter Yan-Tek Hsu. Designing the TFP microprocessor , 1994, IEEE Micro.

[3] Yale N. Patt,et al. A comprehensive instruction fetch mechanism for a processor supporting speculative execution , 1992, MICRO 1992.

[4] R. Mateosian. Power and PowerPC - Principles, Architecture, Implementation [Micro Review] , 1994, IEEE Micro.

[5] Mike Johnson,et al. Superscalar microprocessor design , 1991, Prentice Hall series in innovative technology.

[6] Yale N. Patt,et al. An investigation of the performance of various dynamic scheduling techniques , 1992, MICRO 1992.

[7] Michael D. Smith,et al. Tracing with Pixie , 1991 .

[8] Andrew R. Pleszkun,et al. Implementation of precise interrupts in pipelined processors , 1985, ISCA '98.

[9] Marc Tremblay,et al. UltraSPARC: the next generation superscalar 64-bit SPARC , 1995, Digest of Papers. COMPCON'95. Technologies for the Information Superhighway.