Efficient Embeddings of Binary Trees in VLSI Arrays

We consider the problem of embedding a complete binary tree in squareor hexagonally-connected VLSI arrays Of processing elements (PE's). This problem can be solved in a radically different manner from current layout techniques which are aimed at laying out a given graph in the plane. The difference is due to the fact that a PE can be used both as a tree node and as a connecting element between distant nodes. New embedding schemes are presented in which (asymptotically) 100 percent of the PE's are utilized as tree nodes. This is a significant savings over known schemes, which achieve 50 percent utilization (the well-known H-tree) and 71 percent for some hexagonal schemes. These schemes also speed up signal propagation from the root to the leaves.

[1]  Ellis Horowitz,et al.  The Binary Tree as an Interconnection Network: Applications to Multiprocessor Systems and VLSI , 1981, IEEE Transactions on Computers.

[2]  Melvin A. Breuer,et al.  On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays , 1984, IEEE Transactions on Computers.

[3]  Charles E. Leiserson,et al.  How to assemble tree machines (Extended Abstract) , 1982, STOC '82.

[4]  Lawrence Snyder,et al.  Bounds on minimax edge length for complete binary trees , 1981, STOC '81.

[5]  Israel Koren.  A reconfigurable and fault-tolerant VLSI multiprocessor array , 1981, ISCA '81.

[6]  James B. Orlin,et al.  NP-Completeness for Minimizing Maximum Edge Length in Grid Embeddings , 1985, J. Algorithms.

[7]  Charles E. Leiserson.  Systolic Priority Queues , 1979 .

[8]  Mariagiovanna Sami,et al.  Fault Tolerance Techniques for Array Structures Used in Supercomputing , 1986, Computer.

[9]  Norbert Blum.  An Area-Maximum Edge Length Trade-off for VLSI Layout , 1985, Inf. Control..

[10]  Carlo H. Séquin,et al.  Design considerations for the VLSI processor of X-TREE , 1979, ISCA '79.

[11]  M. Rem,et al.  Cost and performance of VLSI computing structures , 1979, IEEE Transactions on Electron Devices.

[12]  H. T. Kung,et al.  A tree machine for searching problems , 1979 .

[13]  Leslie G. Valiant,et al.  Universality considerations in VLSI circuits , 1981, IEEE Transactions on Computers.

[14]  Frank Thomson Leighton,et al.  Wafer-Scale Integration of Systolic Arrays , 1985, IEEE Trans. Computers.

[15]  Jon Louis Bentley,et al.  Multidimensional Binary Search Trees in Database Applications , 1979, IEEE Transactions on Software Engineering.

[16]  Lawrence Snyder,et al.  Introduction to the configurable, highly parallel computer , 1982, Computer.

[17]  Arnold L. Rosenberg,et al.  The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors , 1983, IEEE Transactions on Computers.

[18]  Charles E. Leiserson,et al.  How to assemble tree machines , 1984 .

[19]  Israel Koren,et al.  Embedding Tree Structures in VLSI Hexagonal Arrays , 1984, IEEE Transactions on Computers.

[20]  Lynn Conway,et al.  Introduction to VLSI systems , 1978 .

[21]  W. L. Ruzzo,et al.  Minimum Edge Length Planar Embeddings of Trees , 1981 .

[22]  H. T. Kung,et al.  On the Area of Binary Tree Layouts , 1980, Inf. Process. Lett..

[23]  Bernard Chazelle,et al.  Census functions: An approach to VLSI upper bounds , 1981, 22nd Annual Symposium on Foundations of Computer Science (sfcs 1981).

[24]  Israel Koren,et al.  Restructuring hexagonal arrays of processors in the presence of faults , 1987 .