On the Simulation of HCI-Induced Variations of IC Timings at High Level

Die shrinking combined with the non-ideal scaling of voltage increases the probability of MOS transistors to encounter HCI. This mechanism causes timing degradation and possibly failures in ICs. The evaluation of timing degradation early in the design flow becomes a must-have to ensure the expected time-to-market and IC lifetime. In this paper, we propose a framework for simulating and analyzing the HCI-induced timing variations at high abstraction level. We first present a bottom-up approach to move information about timing degradation up to the higher abstraction layers. Then, we describe a simulation framework for analyzing the HCI-induced timing variations, and we evaluate its performance and accuracy. Finally, by considering a sample processor, we analyze the impact of the instruction set architecture on slack times and critical paths.

[1]  E. Takeda,et al.  An empirical model for device degradation due to hot-carrier injection , 1983, IEEE Electron Device Letters.

[2]  Sandro Rigo,et al.  ArchC: a systemC-based architecture description language , 2004 .

[3]  Trevor Mudge,et al.  MiBench: A free, commercially representative embedded benchmark suite , 2001 .

[4]  Ulf Schlichtmann,et al.  Aging analysis at gate and macro cell level , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[5]  Spiridon Nikolaidis,et al.  Elimination of Overhead Operations in Complex Loop Structures for Embedded Microprocessors , 2008, IEEE Transactions on Computers.

[6]  Fan Yang,et al.  Statistical reliability analysis under process variation and aging effects , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[7]  Pradip Bose,et al.  A Framework for Architecture-Level Lifetime Reliability Modeling , 2007, 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07).

[8]  K. Seki,et al.  Circuit aging simulator (CAS) , 1988, Technical Digest., International Electron Devices Meeting.

[9]  Rodolfo Azevedo,et al.  Platform designer: An approach for modeling multiprocessor platforms based on SystemC , 2005, Des. Autom. Embed. Syst..

[10]  Vincent Huard,et al.  A bottom-up approach for System-On-Chip reliability , 2011, Microelectron. Reliab..

[11]  Lai-Man Po,et al.  A novel four-step search algorithm for fast block motion estimation , 1996, IEEE Trans. Circuits Syst. Video Technol..

[12]  M.R. de Schultz,et al.  Automatically-retargetable model-driven tools for embedded code inspection in SoCs , 2007, 2007 50th Midwest Symposium on Circuits and Systems.

[13]  Nicolas Ventroux,et al.  Towards a parameterizable cycle-accurate ISS in ArchC , 2010, ACS/IEEE International Conference on Computer Systems and Applications - AICCSA 2010.

[14]  Nicolas Ventroux,et al.  Relation between HCI-induced performance degradation and applications in a RISC processor , 2012, 2012 IEEE 18th International On-Line Testing Symposium (IOLTS).

[15]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[16]  Qiang Xu,et al.  AgeSim: A simulation framework for evaluating the lifetime reliability of processor-based SoCs , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[17]  Yusuf Leblebici,et al.  A simulation methodology for reliability analysis in multi-core SoCs , 2006, GLSVLSI '06.

[18]  Nicolas Ventroux,et al.  A small footprint interleaved multithreaded processor for embedded systems , 2011, 2011 18th IEEE International Conference on Electronics, Circuits, and Systems.

[19]  V. Huard,et al.  Hot-Carrier acceleration factors for low power management in DC-AC stressed 40nm NMOS node at high temperature , 2009, 2009 IEEE International Reliability Physics Symposium.

[20]  Elyse Rosenbaum,et al.  Berkeley reliability tools-BERT , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  Luca Fossati,et al.  ReSP: A non-intrusive Transaction-Level Reflective MPSoC Simulation Platform for design space exploration , 2008, 2008 Asia and South Pacific Design Automation Conference.

[22]  Tushar Gupta,et al.  Impact of Power Consumption and Temperature on Processor Lifetime Reliability , 2012, J. Low Power Electron..

[23]  Nicolas Ventroux,et al.  SESAM extension for fast MPSoC architectural exploration and dynamic streaming applications , 2010, 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip.

[24]  Xiaojun Li,et al.  Electronic circuit reliability modeling , 2006, Microelectron. Reliab..

[25]  Nicolas Ventroux,et al.  SESAM: An MPSoC Simulation Environment for Dynamic Application Processing , 2010, 2010 10th IEEE International Conference on Computer and Information Technology.

[26]  Sarita V. Adve,et al.  AS SCALING THREATENS TO ERODE RELIABILITY STANDARDS, LIFETIME RELIABILITY MUST BECOME A FIRST-CLASS DESIGN CONSTRAINT. MICROARCHITECTURAL INTERVENTION OFFERS A NOVEL WAY TO MANAGE LIFETIME RELIABILITY WITHOUT SIGNIFICANTLY SACRIFICING COST AND PERFORMANCE , 2005 .

[27]  Li Shang,et al.  Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors , 2007, IEEE Micro.

[28]  Sachin S. Sapatnekar,et al.  Scalable Methods for Analyzing the Circuit Failure Probability Due to Gate Oxide Breakdown , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[29]  T. Zimmer,et al.  RAAPS: Reliability Aware ArchC based Processor Simulator , 2010, 2010 IEEE International Integrated Reliability Workshop Final Report.