Transient simulation of on-chip transmission lines via exact pole extraction

An accurate and efficient solution for the transient response at the far end of a transmission line is proposed in this paper. Unlike approximating the poles by truncating the transfer function or matching moments, the exact poles of an interconnect system are analytically extracted. Excellent match is observed between the proposed method and Spectre simulations. With two pairs of poles, the average error for the 50% delay is 1%. Higher accuracy can be obtained with additional pairs of poles. The computational complexity of the model is proportional to the number of pole pairs.

[1]  Lawrence T. Pileggi,et al.  Asymptotic waveform evaluation for timing analysis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Andrew B. Kahng,et al.  An analytical delay model for RLC interconnects , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Guoqing Chen,et al.  An RLC interconnect model based on fourier analysis , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Yungseon Eo,et al.  A traveling-wave-based waveform approximation technique for thetiming verification of single transmission lines , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  James D. Meindl,et al.  Compact distributed RLC interconnect models. I. Single line transient, time delay, and overshoot expressions , 2000 .

[6]  Takayasu Sakurai,et al.  Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs , 1993 .

[7]  James D. Meindl,et al.  Compact distributed RLC interconnect models-Part II: Coupled line transient expressions and peak crosstalk in multilevel networks , 2000 .

[8]  K. Banerjee,et al.  Accurate analysis of on-chip inductance effects and implications for optimal repeater insertion and technology scaling , 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

[9]  Yehea I. Ismail,et al.  Figures of merit to characterize the importance of on-chip inductance , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[10]  Jun Chen,et al.  Piecewise linear model for transmission line with capacitive loading and ramp input , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.